Maximilian Odendahl
Maximilian Odendahl
Verified email at ice.rwth-aachen.de - Homepage
Title
Cited by
Cited by
Year
A compiler infrastructure for embedded heterogeneous MPSoCs
W Sheng, S Schürmans, M Odendahl, M Bertsch, V Volevach, R Leupers, ...
Parallel Computing 40 (2), 51-68, 2014
312014
Automatic calibration of streaming applications for software mapping exploration
W Sheng, S Schurmans, M Odendahl, R Leupers, G Ascheid
System on Chip (SoC), 2011 International Symposium on, 136-142, 2011
172011
Towards energy-aware placement of real-time virtual machines in a cloud data center
N Khalilzad, HR Faragardi, T Nolte
2015 IEEE 17th International Conference on High Performance Computing and …, 2015
152015
Split-cost communication model for improved MPSoC application mapping
M Odendahl, J Castrillon, V Volevach, R Leupers, G Ascheid
2013 International Symposium on System on Chip (SoC), 1-8, 2013
122013
An optimal allocation of memory buffers for complex multicore platforms
A Goens, J Castrillon, M Odendahl, R Leupers
Journal of Systems Architecture 66, 69-83, 2016
82016
A next generation digital signal processor for European space missions
M Odendahl, S Yakoushkin, R Leupers, W Errico, M Donati, L Fanucci
2012 IEEE First AESS European Conference on Satellite Telecommunications …, 2012
62012
Automated code generation of streaming applications for C6000 multicore DSPs
M Odendahl, W Sheng, M Aguilar, R Leupers, G Ascheid
2012 5th European DSP Education and Research Conference (EDERC), 221-224, 2012
62012
Optimized buffer allocation in multicore platforms
M Odendahl, A Goens, R Leupers, G Ascheid, B Ries, B Vocking, ...
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014
52014
DSPACE: a new space DSP development
W Errico, A Colonna, G Piscopiello, P Tosi, B Bacci, V Pii, L Fanucci, ...
ESASP 701, 53, 2012
32012
Extraction of Kahn Process Networks from While Loops in Embedded Software
MA Aguilar, JF Eusse, R Leupers, G Ascheid, M Odendahl
2015 IEEE 17th International Conference on High Performance Computing and …, 2015
22015
DSPACE hardware architecture for on-board real-time image/video processing in European space missions
S Saponara, M Donati, L Fanucci, M Odendahl, R Leupers, W Errico
Real-Time Image and Video Processing 2013 8656, 86560D, 2013
22013
Buffer allocation based on-chip memory optimization for many-core platforms
M Odendahl, A Goens, R Leupers, G Ascheid, T Henriksson
2015 IEEE International Parallel and Distributed Processing Symposium …, 2015
12015
A heuristic for logical data buffer allocation in multicore platforms
B Ries, W Unger, M Odendahl, R Leupers
2014 IEEE 33rd International Performance Computing and Communications …, 2014
12014
A New Space Digital Signal Processor Design
M Donati, S Saponara, L Fanucci, W Errico, A Colonna, G Piscopiello, ...
Applications in Electronics Pervading Industry, Environment and Society, 51-60, 2014
12014
Programming Heterogeneous MPSoCs using MAPS
W Sheng, J Castrillon, A Stulova, M Odendahl, R Leupers, G Ascheid
First International Software Technology Exchange Workshop 2011, 2011
12011
Software optimization for multicore systems
S Schuermans, B Goldschmidt, M Odendahl
US Patent 10,467,120, 2019
2019
Next-generation digital signal processor for European space applications
S Saponara, L Fanucci, M Donati, M Odendahl, R Leupers, W Errico
2013
Digital Signal Processor (DSP) for Space Applications (DSPACE)
A Colonna, G Piscopiello, G Tuccio, W Errico, F Bigongiari, P Tosi, ...
EUROPEAN COMMISSION-DIRECTORATE GENERAL FOR RESEARCH & INNOVATION, 2012
2012
DSPACE: a new space DSP development
A Colonna, G Piscopiello, W Errico, P Tosi, E Cordiviola, B Bacci, V Pii, ...
DASIA 2012 701, 2012
2012
DSPACE–DSP for Space Applications
A Colonna, W Errico, E Cordiviola, S Saponara, L Fanucci, F Reiter, ...
FP7 Space Conference 2011, 2011
2011
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