Takashi NAKADA
Takashi NAKADA
Associate Professor, International Professional University of Technology in Osaka
Verified email at
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Power capping of CPU-GPU heterogeneous systems through coordinating DVFS and task mapping
T Komoda, S Hayashi, T Nakada, S Miwa, H Nakamura
2013 IEEE 31st International Conference on computer design (ICCD), 349-356, 2013
7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write/read-modify-write scheme
H Noguchi, K Ikegami, S Takaya, E Arima, K Kushida, A Kawasumi, ...
2016 IEEE International Solid-State Circuits Conference (ISSCC), 132-133, 2016
An instruction mapping scheme for FU array accelerator
K Yoshimura, T Iwakami, T Nakada, J Yao, H Shimada, Y Nakashima
IEICE TRANSACTIONS on Information and Systems 94 (2), 286-297, 2011
Design and implementation of a workload specific simulator
T Nakada, T Tsumura, H Nakashima
39th Annual Simulation Symposium (ANSS'06), 12 pp.-243, 2006
Normally-off computing project: Challenges and opportunities
H Nakamura, T Nakada, S Miwa
2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), 1-5, 2014
Normally-off computing
T Nakada, H Nakamura
Normally-Off Computing, 57-63, 2017
Design of programmable analog calculation unit by implementing support vector regression for approximate computing
R Zhang, N Uetake, T Nakada, Y Nakashima
IEEE Micro 38 (6), 73-82, 2018
OROCHI: A multiple instruction set SMT processor
T Nakada, Y Nakashima, H Shimada, K Kise, T Kitamura
High-performance and Hardware-aware Computing (HipHaC'08), 1-8, 2008
Design aid of multi-core embedded systems with energy model
T Nakada, K Okamoto, T Komoda, S Miwa, Y Sato, H Ueki, ...
IPSJ Online Transactions 7, 122-131, 2014
Normally-off computing for IoT systems
T Nakada, T Shimizu, H Nakamura
2015 International SoC Design Conference (ISOCC), 147-148, 2015
Immediate sleep: Reducing energy impact of peripheral circuits in STT-MRAM caches
E Arima, H Noguchi, T Nakada, S Miwa, S Takeda, S Fujita, H Nakamura
2015 33rd IEEE International Conference on Computer Design (ICCD), 149-156, 2015
D-MRAM cache: Enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory
H Noguchi, K Nomura, K Abe, S Fujita, E Arima, K Kim, T Nakada, S Miwa, ...
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2013
LAPP: A low power array accelerator with binary compatibility
N Devisetti, T Iwakami, K Yoshimura, T Nakada, J Yao, Y Nakashima
2011 IEEE International Symposium on Parallel and Distributed Processing …, 2011
Energy-efficient continuous task scheduling for near real-time periodic tasks
T Nakada, H Yanagihashi, H Ueki, T Tsuchiya, M Hayashikoshi, ...
2015 IEEE International Conference on Data Science and Data Intensive …, 2015
Proton polarization with naphthalene crystals by integrated solid effect on photoexcited triplet state
M Iinuma, Y Takahashi, I Shaké, M Oda, H M. Shimizu, A Masaike, ...
Journal of the Physical Society of Japan 74 (9), 2622-2630, 2005
Low-power cache memory with state-of-the-art stt-mram for high-performance processors
S Takeda, H Noguchi, K Nomura, S Fujita, S Miwa, E Arima, T Nakada, ...
2015 International SoC Design Conference (ISOCC), 153-154, 2015
Design and implementation of a high speed microprocessor simulator BurstScalar
T Nakada, H Nakashima
The IEEE Computer Society's 12th Annual International Symposium on Modeling …, 2004
Compression and aggregation for optimizing information transmission in distributed CNN
T Mitani, H Fukuoka, Y Hiraga, T Nakada, Y Nakashima
2017 Fifth International Symposium on Computing and Networking (CANDAR), 112-118, 2017
Fine-grain power-gating on STT-MRAM peripheral circuits with locality-aware access control
E Arima, H Noguchi, T Nakada, S Miwa, S Takeda, S Fujita, H Nakamura, ...
The Memory Forum (in conjounction with the 41st International Symposium on …, 2014
Efficient multitasking on fpga using hdl-based checkpointing
HG Vu, T Nakada, Y Nakashima
Applied Reconfigurable Computing. Architectures, Tools, and Applications …, 2018
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