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Hritam Dutta
Hritam Dutta
Professor of Embedded Systems Design, Georg Simon Ohm University of Applied Sciences
Bestätigte E-Mail-Adresse bei th-nuernberg.de
Titel
Zitiert von
Zitiert von
Jahr
PARO: Synthesis of hardware accelerators for multi-dimensional dataflow-intensive applications
F Hannig, H Ruckdeschel, H Dutta, J Teich
Reconfigurable Computing: Architectures, Tools and Applications: 4th …, 2008
842008
A design methodology for hardware acceleration of adaptive filter algorithms in image processing
H Dutta, F Hannig, J Teich, B Heigl, H Hornegger
IEEE 17th International Conference on Application-specific Systems …, 2006
332006
Regular mapping for coarse-grained reconfigurable architectures
F Hannig, H Dutta, J Teich
2004 IEEE International Conference on Acoustics, Speech, and Signal …, 2004
322004
Mapping of regular nested loop programs to coarse-grained reconfigurable arrays-constraints and methodology
F Hannig, H Dutta, J Teich
18th International Parallel and Distributed Processing Symposium, 2004 …, 2004
322004
Co-Design of Massively Parallel Embedded Processor Architectures.
F Hannig, H Dutta, A Kupriyanov, J Teich, R Schaffer, S Siegel, R Merker, ...
ReCoSoC, 27-34, 2005
312005
Hierarchical partitioning for piecewise linear algorithms
H Dutta, F Hannig, J Teich
International Symposium on Parallel Computing in Electrical Engineering …, 2006
292006
A holistic approach for tightly coupled reconfigurable parallel processors
H Dutta, D Kissler, F Hannig, A Kupriyanov, J Teich, B Pottier
Microprocessors and Microsystems 33 (1), 53-62, 2009
282009
Mapping a class of dependence algorithms to coarse-grained reconfigurable arrays: Architectural parameters and methodology
F Hannig, H Dutta, J Teich
International Journal of Embedded Systems 2 (1-2), 114-127, 2006
202006
Model-based synthesis and optimization of static multi-rate image processing algorithms
J Keinert, H Dutta, F Hannig, C Haubelt, J Teich
2009 Design, Automation & Test in Europe Conference & Exhibition, 135-140, 2009
192009
Efficient control generation for mapping nested loop programs onto processor arrays
H Dutta, F Hannig, H Ruckdeschel, J Teich
Journal of Systems Architecture 53 (5-6), 300-309, 2007
142007
Controller synthesis for mapping partitioned programs on array architectures
H Dutta, F Hannig, J Teich
Architecture of Computing Systems-ARCS 2006: 19th International Conference …, 2006
132006
An execution flow for dynamic concurrent systems: simulation of WSN on a Smalltalk/CUDA environment
H Dutta, T Failler, N Melot, B Pottier, S Stinckwich
Proceedings of the SIMPAR 2010 Workshops International Conference on …, 2010
112010
Automatic FIR filter generation for FPGAs
H Ruckdeschel, H Dutta, F Hannig, J Teich
Embedded Computer Systems: Architectures, Modeling, and Simulation: 5th …, 2005
112005
Parallelization approaches for hardware accelerators–loop unrolling versus loop partitioning
F Hannig, H Dutta, J Teich
International Conference on Architecture of Computing Systems, 16-27, 2009
92009
Mapping of nested loop programs onto massively parallel processor arrays with memory and I/O constraints
H Dutta, F Hannig, J Teich, FM auf der Heide, B Monien
Proceedings of the 6th International Heinz Nixdorf Symposium, New Trends in …, 2006
82006
Efficient mapping of multiresolution image filtering algorithms on graphics processors
R Membarth, F Hannig, H Dutta, J Teich
Embedded Computer Systems: Architectures, Modeling, and Simulation: 9th …, 2009
72009
Impact of loop tiling on the controller logic of acceleration engines
H Dutta, J Zhai, F Hannig, J Teich
2009 20th IEEE International Conference on Application-specific Systems …, 2009
62009
Massively parallel processor architectures: a co-design approach
H Dutta, F Hannig, A Kupriyanov, D Kissler, J Teich, R Schaffer, S Siegel, ...
ReCoSoC'07 Reconfigurable Communication-centric Socs, 2007
62007
Efficient mapping of streaming applications for image processing on graphics cards
R Membarth, H Dutta, F Hannig, J Teich
Transactions on High-Performance Embedded Architectures and Compilers V, 1-20, 2019
52019
Synthesis and exploration of loop accelerators for systems-on-a-chip
H Dutta
PQDT-Global, 2011
52011
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