| A 64Gb 533Mb/s DDR interface MLC NAND flash in sub-20nm technology D Lee, IJ Chang, SY Yoon, J Jang, DS Jang, WG Hahn, JY Park, DG Kim, ... 2012 IEEE International Solid-State Circuits Conference, 430-432, 2012 | 51 | 2012 |
| Complementary-FET (CFET) standard cell synthesis framework for design and system technology co-optimization using SMT CK Cheng, CT Ho, D Lee, B Lin, D Park IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (6 …, 2021 | 31 | 2021 |
| SP&R: Simultaneous Placement and Routing framework for standard cell synthesis in sub-7nm D Park, D Lee, I Kang, S Gao, B Lin, CK Cheng 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), 345-350, 2020 | 26 | 2020 |
| PROBE2. 0: A systematic framework for routability assessment from technology to design in advanced nodes CK Cheng, AB Kahng, H Kim, M Kim, D Lee, D Park, M Woo IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021 | 23 | 2021 |
| SP&R: SMT-based simultaneous Place-and-Route for standard cell synthesis of advanced nodes D Lee, D Park, CT Ho, I Kang, H Kim, S Gao, B Lin, CK Cheng IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020 | 23 | 2020 |
| Grid-based framework for routability analysis and diagnosis with conditional design rules D Park, D Lee, I Kang, C Holtz, S Gao, B Lin, CK Cheng IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020 | 19 | 2020 |
| A routability-driven complimentary-FET (CFET) standard cell synthesis framework using SMT CK Cheng, CT Ho, D Lee, D Park Proceedings of the 39th International Conference on Computer-Aided Design, 1-8, 2020 | 16 | 2020 |
| Standard-cell scaling framework with guaranteed pin-accessibility CK Cheng, D Lee, D Park 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020 | 12 | 2020 |
| Multirow complementary-FET (CFET) standard cell synthesis framework using satisfiability modulo theories (SMTs) CK Cheng, CT Ho, D Lee, B Lin IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 7 …, 2021 | 8 | 2021 |
| Smt-based contention-free task mapping and scheduling on smart noc D Lee, B Lin, CK Cheng IEEE Embedded Systems Letters 13 (4), 158-161, 2021 | 7 | 2021 |
| An effective test pattern generation for testing signal integrity Y Kim, MH Yang, Y Park, DY Lee, S Kang 2006 15th Asian Test Symposium, 279-286, 2006 | 6 | 2006 |
| Many-tier vertical gate-all-around nanowire FET standard cell synthesis for advanced technology nodes D Lee, CT Ho, I Kang, S Gao, B Lin, CK Cheng IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 7 …, 2021 | 4 | 2021 |
| An Efficiency Testing Algorithm for Realistic Faults in Dual-Port Memories YK Park, MH Yang, YJ Kim, DY Lee, SH Kang Journal of the Institute of Electronics Engineers of Korea SD 44 (2), 72-85, 2007 | 4 | 2007 |
| Monolithic 3D Semiconductor Footprint Scaling Exploration Based on VFET Standard Cell Layout Methodology, Design Flow, and EDA Platform CK Cheng, CT Ho, D Lee, B Lin IEEE access 10, 65971-65981, 2022 | 3 | 2022 |
| SMT-based contention-free task mapping and scheduling on 2D/3D SMART NoC with mixed dimension-order routing D Lee, B Lin, CK Cheng ACM Transactions on Architecture and Code Optimization (TACO) 19 (1), 1-21, 2021 | 3 | 2021 |
| Core-eco: Concurrent refinement of detailed place-and-route for an efficient eco automation CK Cheng, AB Kahng, I Kang, M Kim, D Lee, B Lin, D Park, M Woo 2021 IEEE 39th International Conference on Computer Design (ICCD), 366-373, 2021 | 3 | 2021 |
| An Effective Test and Diagnosis Algorithm for Dual‐Port Memories Y Park, MH Yang, Y Kim, DY Lee, S Kang ETRI journal 30 (4), 555-564, 2008 | 3 | 2008 |
| A routability-driven complimentary-fet (cfet) standard cell synthesis framework using smt. In 2020 IEEE CK Cheng, CT Ho, D Lee, D Park ACM International Conference On Computer Aided Design (ICCAD), 1-8, 0 | 3 | |
| Machine Learning Prediction for Design and System Technology Co-Optimization Sensitivity Analysis CK Cheng, CT Ho, C Holtz, D Lee, B Lin IEEE Transactions on Very Large Scale Integration (VLSI) Systems 30 (8 …, 2022 | 2 | 2022 |
| Logical Reasoning Techniques for VLSI Applications D Lee University of California, San Diego, 2022 | 2 | 2022 |
