フォロー
Anuj Verma
Anuj Verma
Ph.D Research Scholar
確認したメール アドレス: students.iitmandi.ac.in
タイトル
引用先
引用先
年
A new VLSI architecture of next-generation QC-LDPC decoder for 5G new-radio wireless-communication standard
A Verma, R Shrestha
2020 IEEE international symposium on circuits and systems (ISCAS), 1-5, 2020
152020
A new partially-parallel VLSI-architecture of quasi-cyclic LDPC decoder for 5G new-radio
A Verma, R Shrestha
2020 33rd International Conference on VLSI Design and 2020 19th …, 2020
142020
Low computational-complexity SOMS-algorithm and high-throughput decoder architecture for QC-LDPC codes
A Verma, R Shrestha
IEEE Transactions on Vehicular Technology 72 (1), 66-80, 2022
132022
Hardware-efficient and high-throughput LLRC segregation based binary QC-LDPC decoding algorithm and architecture
A Verma, R Shrestha
IEEE Transactions on Circuits and Systems II: Express Briefs 68 (8), 2835-2839, 2021
72021
A New VLSI Architecture of Next-Generation QC-LDPC Decoder for 5G New-Radio Wireless-Communication Standard
A Verma, R Shrestha
VLSID 2020
A Verma, R Shrestha, V Tyagi, V Rana, F Loh, KK Saluja
現在システムで処理を実行できません。しばらくしてからもう一度お試しください。
論文 1–6