| Toward an open-source digital flow: First learnings from the openroad project T Ajayi, VA Chhabria, M Fogaça, S Hashemi, A Hosny, AB Kahng, M Kim, ... Proceedings of the 56th Annual Design Automation Conference 2019, 1-4, 2019 | 143 | 2019 |
| A 1Mb 28nm STT-MRAM with 2.8 ns read access time at 1.2 V VDD using single-cap offset-cancelled sense amplifier and in-situ self-write-termination Q Dong, Z Wang, J Lim, Y Zhang, YC Shih, YD Chih, J Chang, D Blaauw, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 480-482, 2018 | 86 | 2018 |
| A 1-Mb 28-nm 1T1MTJ STT-MRAM With Single-Cap Offset-Cancelled Sense Amplifier and In Situ Self-Write-Termination Q Dong, Z Wang, J Lim, Y Zhang, ME Sinangil, YC Shih, YD Chih, ... IEEE Journal of Solid-State Circuits 54 (1), 231-239, 2018 | 55 | 2018 |
| A 28NM integrated true random number generator harvesting entropy from MRAM K Yang, Q Dong, Z Wang, YC Shih, YD Chih, J Chang, D Blaauw, ... 2018 IEEE Symposium on VLSI Circuits, 171-172, 2018 | 48 | 2018 |
| RRAM-DNN: An RRAM and model-compression empowered all-weights-on-chip DNN accelerator Z Li, Z Wang, L Xu, Q Dong, B Liu, CI Su, WT Chu, G Tsou, YD Chih, ... IEEE Journal of Solid-State Circuits 56 (4), 1105-1115, 2020 | 24 | 2020 |
| An all-weights-on-chip dnn accelerator in 22nm ull featuring 24× 1 mb erram Z Wang, Z Li, L Xu, Q Dong, CI Su, WT Chu, G Tsou, YD Chih, TYJ Chang, ... 2020 IEEE Symposium on VLSI Circuits, 1-2, 2020 | 11 | 2020 |
| A 22nm 3.5 TOPS/W Flexible Micro-Robotic Vision SoC with 2MB eMRAM for Fully-on-Chip Intelligence Q Zhang, H An, Z Fan, Z Wang, Z Li, G Wang, HS Kim, D Blaauw, ... 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022 | 9 | 2022 |
| Audio and Image Cross-Modal Intelligence via a 10TOPS/W 22nm SoC with Back-Propagation and Dynamic Power Gating Z Fan, H An, Q Zhang, B Xu, L Xu, CW Tseng, Y Peng, A Cao, B Liu, ... 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022 | 5 | 2022 |
| AA-ResNet: Energy efficient all-analog resnet accelerator J Lim, M Choi, B Liu, T Kang, Z Li, Z Wang, Y Zhang, K Yang, D Blaauw, ... 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems …, 2020 | 5 | 2020 |
| A High-Throughput Pruning-Based Pair-Hidden-Markov-Model Hardware Accelerator for Next-Generation DNA Sequencing X Wu, A Subramaniyan, Z Wang, S Narayanasamy, R Das, D Blaauw IEEE Solid-State Circuits Letters 4, 31-35, 2020 | 4 | 2020 |
| 17.3 GCUPS pruning-based pair-hidden-Markov-model accelerator for next-generation DNA sequencing X Wu, A Subramaniyan, Z Wang, S Narayanasamy, R Das, D Blaauw 2020 IEEE Symposium on VLSI Circuits, 1-2, 2020 | 2 | 2020 |
| A 2.46 m reads/s genome sequencing accelerator using a 625 processing-element array Z Wang, T Zhang, D Fujiki, A Subramaniyan, X Wu, M Yasuda, S Miyoshi, ... 2020 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2020 | 2 | 2020 |
| Energy Efficient Adiabatic FRAM with 0.99 PJ/Bit Write for IoT Applications S Jeloka, Z Wang, R Xie, S Khanna, S Bartling, D Sylvester, D Blaauw 2018 IEEE Symposium on VLSI Circuits, 85-86, 2018 | 2 | 2018 |
| Hardware Acceleration for Third-Generation FHE and PSI Based on It Z Wang, D Sylvester, HS Kim, D Blaauw arXiv preprint arXiv:2204.11334, 2022 | | 2022 |
| A 2.46 M Reads/s Seed-Extension Accelerator for Next-Generation Sequencing Using a String-Independent PE Array Z Wang, T Zhang, D Fujiki, A Subramaniyan, X Wu, M Yasuda, S Miyoshi, ... IEEE Journal of Solid-State Circuits 56 (3), 824-833, 2020 | | 2020 |
| A kind of numerical model analysis neural network chip architecture 朱晓雷,应曌中,罗冲,王喆鸿,王昭余好雨 CN Patent CN105,930,903 B, 2018 | | 2018 |
David BlaauwProfessor of Electrical Engineering and Computer Science, University of MichiganVerified email at umich.edu
