| A lean, low power, low latency DRAM memory controller for transprecision computing C Sudarshan, J Lappas, C Weis, DM Mathew, M Jung, N Wehn Embedded Computer Systems: Architectures, Modeling, and Simulation: 19th …, 2019 | 20 | 2019 |
| An in-dram neural network processing engine C Sudarshan, J Lappas, MM Ghaffar, V Rybalkin, C Weis, M Jung, ... 2019 IEEE international symposium on circuits and systems (ISCAS), 1-5, 2019 | 17 | 2019 |
| Efficient hardware architectures for 1D-and MD-LSTM networks V Rybalkin, C Sudarshan, C Weis, J Lappas, N Wehn, L Cheng Journal of Signal Processing Systems 92, 1219-1245, 2020 | 12 | 2020 |
| Revisiting pass-transistor logic styles in a 12nm finfet technology node J Lappas, A Chinazzo, C Weis, C Xia, Z Wu, L Ni, N Wehn 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2022 | 4 | 2022 |
| A weighted current summation based mixed signal DRAM-PIM architecture for deep neural network inference C Sudarshan, T Soliman, J Lappas, C Weis, MH Sadi, M Jung, A Guntoro, ... IEEE Journal on Emerging and Selected Topics in Circuits and Systems 12 (2 …, 2022 | 3 | 2022 |
| A novel DRAM architecture for improved bandwidth utilization and latency reduction using dual-page operation C Sudarshan, L Steiner, M Jung, J Lappas, C Weis, N Wehn IEEE Transactions on Circuits and Systems II: Express Briefs 68 (5), 1615-1619, 2021 | 3 | 2021 |
| Investigation of Pass Transistor Logic in a 12nm FinFET CMOS Technology AL Chinazzo, J Lappas, C Weis, Q Huang, Z Wu, L Ni, N Wehn 2022 29th IEEE International Conference on Electronics, Circuits and Systems …, 2022 | 2 | 2022 |
| Correction to: efficient hardware architectures for 1D-and MD-LSTM networks V Rybalkin, C Sudarshan, C Weis, J Lappas, N Wehn, L Cheng Journal of Signal Processing Systems 93, 1467-1467, 2021 | 2 | 2021 |
| A7. 4-cell optimization for the iisic cmos-chip serving as a front-end for integrated impedance spectroscopy A Renner, J Lappas, A König Proceedings SENSOR 2015, 166-171, 2015 | 2 | 2015 |
| Machine learning based soft error rate estimation of pass transistor logic in high-speed communication Z Zhang, J Lappas, A Chinazzo, C Weis, Z Wu, L Ni, N Wehn, M Tahoori 2022 IEEE European Test Symposium (ETS), 1-4, 2022 | 1 | 2022 |
| Timing Analysis beyond Complementary CMOS Logic Styles J Lappas, MA Riahi, C Weis, N Wehn, S Nassif 2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC), 189-194, 2024 | | 2024 |
