| Synthesis of reversible circuits with minimal lines for large functions M Soeken, R Wille, C Hilken, N Przigoda, R Drechsler 2012 17th Asia and South Pacific Design Automation Conference (ASP-DAC), 85-92, 2012 | 126 | 2012 |
| Analyzing Inconsistencies in UML/OCL Models N Przigoda, R Wille, R Drechsler Journal of Circuits, Systems and Computers 25 (03), 1640021, 2016 | 59 | 2016 |
| Exact synthesis of Toffoli gate circuits with negative control lines R Wille, M Soeken, N Przigoda, R Drechsler 2012 IEEE 42nd International Symposium on Multiple-Valued Logic (ISMVL), 69-74, 2012 | 37 | 2012 |
| Checking concurrent behavior in UML/OCL models N Przigoda, C Hilken, R Wille, J Peleska, R Drechsler 2015 ACM/IEEE 18th International Conference on Model Driven Engineering …, 2015 | 23 | 2015 |
| Ground Setting Properties for an Efficient Translation of OCL in SMT-based Model Finding N Przigoda, R Wille, R Drechsler 2016 ACM/IEEE 19th International Conference on Model Driven Engineering …, 2016 | 22 | 2016 |
| A Generic Representation of CCSL Time Constraints for UML/MARTE Models J Peters, R Wille, N Przigoda, U Kuhne, R Drechsler Design Automation Conference (DAC), 2015 52nd ACM/EDAC/IEEE, 1-6, 2015 | 21 | 2015 |
| Verifying the structure and behavior in UML/OCL models using satisfiability solvers N Przigoda, M Soeken, R Wille, R Drechsler IET Cyber-Physical Systems: Theory & Applications 1 (1), 49-59, 2016 | 19 | 2016 |
| Contradiction analysis for inconsistent formal models N Przigoda, R Wille, R Drechsler 2015 IEEE 18th International Symposium on Design and Diagnostics of …, 2015 | 17 | 2015 |
| Frame Conditions in Symbolic Representations of UML/OCL Models N Przigoda, J Gomes Filho, P Niemann, R Wille, R Drechsler 14th ACM-IEEE International Conference on Formal Methods and Models for …, 2016 | 13 | 2016 |
| Verification-driven design across abstraction levels: A case study N Przigoda, J Stoppe, J Seiter, R Wille, R Drechsler 2015 Euromicro Conference on Digital System Design, 375-382, 2015 | 12 | 2015 |
| Fault Detection in Parity Preserving Reversible Circuits N Przigoda, G Dueck, R Wille, R Drechsler 46nd IEEE International Symposium on Multiple-Valued Logic (ISMVL), 2016 | 11 | 2016 |
| Towards a Verification Flow Across Abstraction Levels: Verifying Implementations Against Their Formal Specification P Gonzalez-de-Aledo, N Przigoda, R Wille, R Drechsler, P Sanchez IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016 | 10 | 2016 |
| Integrating an SMT-based Model Finder into USE N Przigoda, F Hilken, J Peters, R Wille, M Gogolla, R Drechsler Workshop on Model-Driven Engineering, Verification, and Validation (MoDeVVa), 2016 | 8 | 2016 |
| Leveraging the analysis for invariant independence in formal system models N Przigoda, R Wille, R Drechsler 2015 Euromicro Conference on Digital System Design, 359-366, 2015 | 8 | 2015 |
| Automated Validation & Verification of UML/OCL Models Using Satisfiability Solvers N Przigoda, R Wille, J Przigoda, R Drechsler Springer, 2018 | 7 | 2018 |
| A compact and efficient SAT encoding for quantum circuits R Wille, N Przigoda, R Drechsler 2013 Africon, 1-6, 2013 | 6 | 2013 |
| Verbesserung der Fehlersuche in inkonsistenten formalen Modellen (Erweiterte Zusammenfassung). N Przigoda, R Wille, R Drechsler MBMV, 165-172, 2015 | 5 | 2015 |
| More than true or false N Przigoda, P Niemann, J Peters, F Hilken, R Wille, R Drechsler Proceedings of the 15th ACM-IEEE International Conference on Formal Methods …, 2017 | 4* | 2017 |
| Clocks vs. Instants Relations: Verifying CCSL Time Constraints in UML/MARTE Models J Peters, N Przigoda, R Wille, R Drechsler 14th ACM-IEEE International Conference on Formal Methods and Models for …, 2016 | 4 | 2016 |
| Towards an Automatic Approach for Restricting UML/OCL Invariability Clauses N Przigoda, J Peters, M Soeken, R Wille, R Drechsler Proceedings of the 12th Workshop on Model-Driven Engineering, Verification …, 2015 | 4 | 2015 |
Robert WilleJohannes Kepler University LinzBestätigte E-Mail-Adresse bei jku.at
