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Nils Przigoda
Nils Przigoda
Bestätigte E-Mail-Adresse bei informatik.uni-bremen.de
Titel
Zitiert von
Zitiert von
Jahr
Synthesis of reversible circuits with minimal lines for large functions
M Soeken, R Wille, C Hilken, N Przigoda, R Drechsler
2012 17th Asia and South Pacific Design Automation Conference (ASP-DAC), 85-92, 2012
1352012
Analyzing Inconsistencies in UML/OCL Models
N Przigoda, R Wille, R Drechsler
Journal of Circuits, Systems and Computers 25 (03), 1640021, 2016
672016
Exact synthesis of Toffoli gate circuits with negative control lines
R Wille, M Soeken, N Przigoda, R Drechsler
2012 IEEE 42nd International Symposium on Multiple-Valued Logic (ISMVL), 69-74, 2012
422012
A Generic Representation of CCSL Time Constraints for UML/MARTE Models
J Peters, R Wille, N Przigoda, U Kuhne, R Drechsler
Design Automation Conference (DAC), 2015 52nd ACM/EDAC/IEEE, 1-6, 2015
282015
Verifying the structure and behavior in UML/OCL models using satisfiability solvers
N Przigoda, M Soeken, R Wille, R Drechsler
IET Cyber-Physical Systems: Theory & Applications 1 (1), 49-59, 2016
262016
Ground Setting Properties for an Efficient Translation of OCL in SMT-based Model Finding
N Przigoda, R Wille, R Drechsler
2016 ACM/IEEE 19th International Conference on Model Driven Engineering …, 2016
242016
Checking concurrent behavior in UML/OCL models
N Przigoda, C Hilken, R Wille, J Peleska, R Drechsler
2015 ACM/IEEE 18th International Conference on Model Driven Engineering …, 2015
222015
Contradiction analysis for inconsistent formal models
N Przigoda, R Wille, R Drechsler
2015 IEEE 18th International Symposium on Design and Diagnostics of …, 2015
172015
A compact and efficient SAT encoding for quantum circuits
R Wille, N Przigoda, R Drechsler
2013 Africon, 1-6, 2013
152013
Frame Conditions in Symbolic Representations of UML/OCL Models
N Przigoda, J Gomes Filho, P Niemann, R Wille, R Drechsler
14th ACM-IEEE International Conference on Formal Methods and Models for …, 2016
132016
Fault Detection in Parity Preserving Reversible Circuits
N Przigoda, G Dueck, R Wille, R Drechsler
46nd IEEE International Symposium on Multiple-Valued Logic (ISMVL), 2016
122016
Verification-driven design across abstraction levels: A case study
N Przigoda, J Stoppe, J Seiter, R Wille, R Drechsler
2015 Euromicro Conference on Digital System Design, 375-382, 2015
122015
Towards a Verification Flow Across Abstraction Levels: Verifying Implementations Against Their Formal Specification
P Gonzalez-de-Aledo, N Przigoda, R Wille, R Drechsler, P Sanchez
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016
102016
Automated Validation & Verification of UML/OCL Models Using Satisfiability Solvers
N Przigoda, R Wille, J Przigoda, R Drechsler
Springer, 2018
92018
Integrating an SMT-based Model Finder into USE
N Przigoda, F Hilken, J Peters, R Wille, M Gogolla, R Drechsler
Workshop on Model-Driven Engineering, Verification, and Validation (MoDeVVa), 2016
92016
Clocks vs. Instants Relations: Verifying CCSL Time Constraints in UML/MARTE Models
J Peters, N Przigoda, R Wille, R Drechsler
14th ACM-IEEE International Conference on Formal Methods and Models for …, 2016
92016
Leveraging the analysis for invariant independence in formal system models
N Przigoda, R Wille, R Drechsler
2015 Euromicro Conference on Digital System Design, 359-366, 2015
82015
Frame conditions in the automatic validation and verification of UML/OCL models: A symbolic formulation of modifies only statements
N Przigoda, P Niemann, J Gomes Filho, R Wille, R Drechsler
Computer Languages, Systems & Structures 54, 512-527, 2018
72018
Optimal Railway Routing Using Virtual Subsections
T Peham, J Przigoda, N Przigoda, R Wille
International Conference on Reliability, Safety, and Security of Railway …, 2022
62022
Towards Automatic Design and Verification for Level 3 of the European Train Control System
R Wille, T Peham, J Przigoda, N Przigoda
Design, Automation, and Test in Europe (DATE), 2021
62021
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