Dyer Rolán García
Dyer Rolán García
Verification engineer at ARM
Bestätigte E-Mail-Adresse bei udc.es
Zitiert von
Zitiert von
Adaptive line placement with the set balancing cache
D Rolán, BB Fraguela, R Doallo
Proceedings of the 42nd Annual IEEE/ACM International Symposium on …, 2009
Adaptive set-granular cooperative caching
D Rolan, BB Fraguela, R Doallo
IEEE International Symposium on High-Performance Comp Architecture, 1-12, 2012
Reducing capacity and conflict misses using set saturation levels
D Rolán, BB Fraguela, R Doallo
2010 International Conference on High Performance Computing, 1-9, 2010
Method, apparatus and system to cache sets of tags of an off-die cache memory
D Rolan, N Hyuseinova, BA Cuesta, Q Cai
US Patent 9,558,120, 2017
Memory imbalance prediction based cache management
Q Cai, D Rolan, B Cuesta, F Zyulkyarov, S Ozdemir, M Nicolaides
US Patent 9,286,237, 2016
A fine‐grained thread‐aware management policy for shared caches
D Rolán, D Andrade, BB Fraguela, R Doallo
Concurrency and Computation: Practice and Experience 26 (6), 1355-1374, 2014
Virtually split cache: An efficient mechanism to distribute instructions and data
D Rolán, BB Fraguela, R Doallo
ACM Transactions on Architecture and Code Optimization (TACO) 10 (4), 1-24, 2013
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