Venkata Rajesh Pamula
Title
Cited by
Cited by
Year
22.4 A 172µW compressive sampling photoplethysmographic readout with embedded direct heart-rate and variability extraction from compressively sampled data
PV Rajesh, JM Valero-Sarmiento, L Yan, A Bozkurt, C Van Hoof, ...
2016 IEEE International Solid-State Circuits Conference (ISSCC), 386-387, 2016
412016
A 680 nA ECG acquisition IC for leadless pacemaker applications
L Yan, P Harpe, VR Pamula, M Osawa, Y Harada, K Tamiya, C Van Hoof, ...
IEEE transactions on biomedical circuits and systems 8 (6), 779-786, 2014
342014
A 172 W Compressively Sampled Photoplethysmographic (PPG) Readout ASIC With Heart Rate Estimation Directly From Compressively Sampled Data
VR Pamula, JM Valero-Sarmiento, L Yan, A Bozkurt, C Van Hoof, ...
IEEE transactions on biomedical circuits and systems 11 (3), 487-496, 2017
312017
A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0 V cortex-M0 processor
X Sun, S Kim, F ur Rahman, VR Pamula, X Li, N John, VS Sathe
2018 IEEE International Solid-State Circuits Conference-(ISSCC), 302-304, 2018
132018
A novel feature extraction algorithm for on the sensor node processing of compressive sampled photoplethysmography signals
VR Pamula, M Verhelst, C Van Hoof, RF Yazicioglu
2015 IEEE SENSORS, 1-4, 2015
132015
Computationally-efficient compressive sampling for low-power pulseoximeter system
VR Pamula, M Verhelst, C Van Hoof, RF Yazicioglu
2014 IEEE Biomedical Circuits and Systems Conference (BioCAS) Proceedings, 69-72, 2014
122014
14.5 A 0.6-to-1.1 V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS
X Sun, A Boora, W Zhang, VR Pamula, V Sathe
2019 IEEE International Solid-State Circuits Conference-(ISSCC), 230-232, 2019
112019
A unified clock and switched-capacitor-based power delivery architecture for variation tolerance in low-voltage SoC domains
F ur Rahman, S Kim, N John, R Kumar, X Li, R Pamula, KA Bowman, ...
IEEE Journal of Solid-State Circuits 54 (4), 1173-1184, 2019
102019
An all-digital true-random-number generator with integrated de-correlation and bias correction at 3.2-to-86 Mb/s, 2.58 pJ/bit in 65-nm CMOS
VR Pamula, X Sun, S Kim, F ur Rahman, B Zhang, VS Sathe
2018 IEEE Symposium on VLSI Circuits, 1-2, 2018
102018
An all-digital unified clock frequency and switched-capacitor voltage regulator for variation tolerance in a sub-threshold ARM cortex M0 processor
FU Rahman, S Kim, N John, R Kumar, X Li, R Pamula, KA Bowman, ...
2018 IEEE Symposium on VLSI Circuits, 65-66, 2018
82018
Architecture considerations for stochastic computing accelerators
VT Lee, A Alaghi, R Pamula, VS Sathe, L Ceze, M Oskin
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
72018
19.1 Computationally Enabled Total Energy Minimization Under Performance Requirements for a Voltage-Regulated 0.38-to-0.58 V Microprocessor in 65nm CMOS
F ur Rahman, R Pamula, A Boora, X Sun, V Sathe
2019 IEEE International Solid-State Circuits Conference-(ISSCC), 312-314, 2019
52019
Vacuum generating device
HY Cho
US Patent 6,729,851, 2004
5*2004
A wearable wrist-band with compressive sensing based ultra-low power photoplethysmography readout circuit
P Ahmmed, J Dieffenderfer, JM Valero-Sarmiento, VR Pamula, ...
2019 IEEE 16th International Conference on Wearable and Implantable Body …, 2019
42019
An ultra-low power, robust photoplethysmographic readout exploiting compressive sampling, artifact reduction, and sensor fusion
VR Pamula, C Van Hoof, M Verhelst
Hybrid ADCs, Smart Sensors for the IoT, and Sub-1V & Advanced Node Analog …, 2018
42018
Model based development of the digital part of a rfid transponder with xilinx system generator for a fpga platform
VR Pamula, W Strauß, J Bernhard
2012 Fourth International EURASIP Workshop on RFID Technology, 124-127, 2012
42012
System and method for heart rate detection with motion artifact reduction
VR Pamula, M Verhelst
US Patent 10,709,389, 2020
32020
A 0.0023 mm/ch. Delta-Encoded, Time-Division Multiplexed Mixed-Signal ECoG Recording Architecture With Stimulus Artifact Suppression
JP Uehlin, WA Smith, VR Pamula, SI Perlmutter, JC Rudell, VS Sathe
IEEE Transactions on Biomedical Circuits and Systems 14 (2), 319-331, 2019
32019
A Bidirectional Brain Computer Interface with 64-Channel Recording, Resonant Stimulation and Artifact Suppression in Standard 65nm CMOS
J Uehlin, WA Smith, VR Pamula, S Perlmutter, V Sathe, JC Rudell
ESSCIRC 2019-IEEE 45th European Solid State Circuits Conference (ESSCIRC), 77-80, 2019
32019
An All-Digital Fused PLL-Buck Architecture for 82% Average Vdd-Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor
X Sun, F ur Rahman, VR Pamula, S Kim, X Li, N John, VS Sathe
IEEE Journal of Solid-State Circuits 54 (11), 3215-3225, 2019
32019
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