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Francesco Restuccia
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Is your bus arbiter really fair? restoring fairness in AXI interconnects for FPGA SoCs
F Restuccia, M Pagani, A Biondi, M Marinoni, G Buttazzo
ACM Transactions on Embedded Computing Systems (TECS) 18 (5s), 1-22, 2019
362019
AXI hyperconnect: A predictable, hypervisor-level interconnect for hardware accelerators in FPGA SoC
F Restuccia, A Biondi, M Marinoni, G Cicero, G Buttazzo
2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020
352020
AKER: A design and verification framework for safe and secure soc access control
F Restuccia, A Meza, R Kastner
2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1-9, 2021
242021
Modeling and analysis of bus contention for hardware accelerators in FPGA SoCs
F Restuccia, M Pagani, A Biondi, M Marinoni, G Buttazzo
32nd Euromicro Conference on Real-Time Systems (ECRTS 2020), 2020
232020
Time-predictable acceleration of deep neural networks on fpga soc platforms
F Restuccia, A Biondi
2021 IEEE Real-Time Systems Symposium (RTSS), 441-454, 2021
192021
Quality-of-service implications of enhanced program algorithms for charge-trapping NAND in future solid-state drives
A Grossi, L Zuolo, F Restuccia, C Zambelli, P Olivo
IEEE Transactions on Device and Materials Reliability 15 (3), 363-369, 2015
192015
Safely preventing unbounded delays during bus transactions in FPGA-based SoC
F Restuccia, A Biondi, M Marinoni, G Buttazzo
2020 IEEE 28th Annual International Symposium on Field-Programmable Custom …, 2020
182020
Isadora: Automated information flow property generation for hardware designs
C Deutschbein, A Meza, F Restuccia, R Kastner, C Sturton
Proceedings of the 5th Workshop on Attacks and Solutions in Hardware …, 2021
132021
A remote control system for emergency ventilators during SARS-CoV-2
M Barrow, F Restuccia, M Gobulukoglu, E Rossi, R Kastner
IEEE embedded systems letters 14 (1), 43-46, 2021
122021
Security verification of the opentitan hardware root of trust
A Meza, F Restuccia, J Oberg, D Rizzo, R Kastner
IEEE Security & Privacy, 2023
82023
A framework for design, verification, and management of SoC access control systems
F Restuccia, A Meza, R Kastner, J Oberg
IEEE Transactions on Computers 72 (2), 386-400, 2022
62022
Toward hardware security property generation at scale
C Deutschbein, A Meza, F Restuccia, M Gregoire, R Kastner, C Sturton
IEEE Security & Privacy 20 (3), 43-51, 2022
62022
Hardware Acceleration of Deep Neural Networks for Autonomous Driving on FPGA-based SoC
G Sciangula, F Restuccia, A Biondi, G Buttazzo
2022 25th Euromicro Conference on Digital System Design (DSD), 2022
52022
PAC-PL: Enabling control-flow integrity with pointer authentication in FPGA SoC platforms
G Serra, P Fara, G Cicero, F Restuccia, A Biondi
2022 IEEE 28th Real-Time and Embedded Technology and Applications Symposium …, 2022
52022
Isadora: automated information-flow property generation for hardware security verification
C Deutschbein, A Meza, F Restuccia, R Kastner, C Sturton
Journal of Cryptographic Engineering 13 (4), 391-407, 2023
42023
Safety verification of third-party hardware modules via information flow tracking
A Meza, F Restuccia, R Kastner, J Oberg
1st Real-time And intelliGent Edge computing workshop (RAGE) co-located with …, 2022
42022
Automating hardware security property generation
R Kastner, F Restuccia, A Meza, S Ray, J Fung, C Sturton
Proceedings of the 59th ACM/IEEE Design Automation Conference, 1384-1387, 2022
42022
Cut and forward: Safe and secure communication for FPGA system on chips
F Restuccia, R Kastner
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2022
32022
Bounding Memory Access Times in Multi-Accelerator Architectures on FPGA SoCs
F Restuccia, M Pagani, A Biondi, M Marinoni, G Buttazzo
IEEE Transactions on Computers 72 (1), 154-167, 2022
22022
ARTe: Providing real-time multitasking to Arduino
F Restuccia, M Pagani, A Mascitti, M Barrow, M Marinoni, A Biondi, ...
Journal of Systems and Software 186, 111185, 2022
22022
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