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Shivam Bhasin
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{CSI}{NN}: Reverse Engineering of Neural Network Architectures Through Electromagnetic Side Channel
L Batina, S Bhasin, D Jap, S Picek
28th {USENIX} Security Symposium ({USENIX} Security 19), 515-532, 2019
194*2019
Make Some Noise. Unleashing the Power of Convolutional Neural Networks for Profiled Side-channel Analysis
J Kim, S Picek, A Heuser, S Bhasin, A Hanjalic
IACR Transactions on Cryptographic Hardware and Embedded Systems, 148-179, 2019
1922019
The curse of class imbalance and conflicting metrics with machine learning for side-channel evaluations
S Picek, A Heuser, A Jovic, S Bhasin, F Regazzoni
IACR Transactions on Cryptographic Hardware and Embedded Systems 2019 (1), 1-29, 2019
1682019
Hardware Trojan Horses in Cryptographic IP Cores
S Bhasin, JL Danger, S Guilley, XT Ngo, L Sauvage
Fault Diagnosis and Tolerance in Cryptography (FDTC), 2013 Workshop on, 15-29, 2013
1472013
BCDL: a high speed balanced DPL for FPGA with global precharge and no early evaluation
M Nassar, S Bhasin, JL Danger, G Duc, S Guilley
Proceedings of the Conference on Design, Automation and Test in Europe, 849-854, 2010
1122010
A survey on hardware trojan detection techniques
S Bhasin, F Regazzoni
Circuits and Systems (ISCAS), 2015 IEEE International Symposium on, 2021-2024, 2015
1012015
NICV: Normalized Inter-Class Variance for Detection of Side-Channel Leakage.
S Bhasin, JL Danger, S Guilley, Z Najm
IACR Cryptology ePrint Archive 2013, 717, 2013
942013
On the performance of convolutional neural networks for side-channel analysis
S Picek, IP Samiotis, J Kim, A Heuser, S Bhasin, A Legay
International Conference on Security, Privacy, and Applied Cryptography …, 2018
932018
Practical fault attack on deep neural networks
J Breier, X Hou, D Jap, L Ma, S Bhasin, Y Liu
Proceedings of the 2018 ACM SIGSAC Conference on Computer and Communications …, 2018
922018
Generic Side-channel attacks on CCA-secure lattice-based PKE and KEMs
P Ravi, SS Roy, A Chattopadhyay, S Bhasin
IACR Transactions on Cryptographic Hardware and Embedded Systems, 307-335, 2020
872020
Linear complementary dual code improvement to strengthen encoded circuit against hardware Trojan horses
XT Ngo, S Bhasin, JL Danger, S Guilley, Z Najm
Hardware Oriented Security and Trust (HOST), 2015 IEEE International …, 2015
752015
Persistent Fault Analysis on Block Ciphers
F Zhang, X Lou, X Zhao, S Bhasin, W He, R Ding, S Qureshi, K Ren
IACR Transactions on Cryptographic Hardware and Embedded Systems, 150-172, 2018
742018
Overview of dual rail with precharge logic styles to thwart implementation-level attacks on hardware cryptoprocessors
JL Danger, S Guilley, S Bhasin, M Nassar
Signals, Circuits and Systems (SCS), 2009 3rd International Conference on, 1-8, 2009
702009
WDDL is protected against setup time violation attacks
N Selmane, S Bhasin, S Guilley, T Graba, JL Danger
Fault Diagnosis and Tolerance in Cryptography (FDTC), 2009 Workshop on, 73-83, 2009
682009
Mind the portability: A warriors guide through realistic profiled side-channel analysis
S Bhasin, A Chattopadhyay, A Heuser, D Jap, S Picek, R Ranjan
NDSS 2020-Network and Distributed System Security Symposium, 1-14, 2020
592020
Hardware trojan detection by delay and electromagnetic measurements
XT Ngo, I Exurville, S Bhasin, JL Danger, S Guilley, Z Najm, JB Rigaud, ...
Proceedings of the 2015 Design, Automation & Test in Europe Conference …, 2015
572015
Toward Threat of Implementation Attacks on Substation Security: Case Study on Fault Detection and Isolation
A Chattopadhyay, A Ukil, D Jap, S Bhasin
IEEE Transactions on Industrial Informatics 14 (6), 2442-2451, 2018
542018
Analysis and improvements of the DPA contest v4 implementation
S Bhasin, N Bruneau, JL Danger, S Guilley, Z Najm
International Conference on Security, Privacy, and Applied Cryptography …, 2014
512014
Side-channel leakage and trace compression using normalized inter-class variance
S Bhasin, JL Danger, S Guilley, Z Najm
Proceedings of the Third Workshop on Hardware and Architectural Support for …, 2014
452014
Countering early evaluation: an approach towards robust dual-rail precharge logic
S Bhasin, S Guilley, F Flament, N Selmane, JL Danger
Proceedings of the 5th Workshop on Embedded Systems Security, 6, 2010
452010
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