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Frank Hannig
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HIPAcc: A Domain-Specific Language and Compiler for Image Processing
R Membarth, O Reiche, F Hannig, J Teich, M Körner, W Eckert
IEEE Transactions on Parallel and Distributed Systems 27 (1), 210-224, 2015
1302015
Trends in data locality abstractions for HPC systems
D Unat, A Dubey, T Hoefler, J Shalf, M Abraham, M Bianco, ...
IEEE Transactions on Parallel and Distributed Systems 28 (10), 3007-3020, 2017
1042017
A highly parameterizable parallel processor array architecture
D Kissler, F Hannig, A Kupriyanov, J Teich
2006 IEEE International Conference on Field Programmable Technology, 105-112, 2006
982006
Invasive tightly-coupled processor arrays: A domain-specific architecture/compiler co-design approach
F Hannig, V Lari, S Boppu, A Tanase, O Reiche
ACM Transactions on Embedded Computing Systems (TECS) 13 (4s), 1-29, 2014
902014
PARO: Synthesis of hardware accelerators for multi-dimensional dataflow-intensive applications
F Hannig, H Ruckdeschel, H Dutta, J Teich
Reconfigurable Computing: Architectures, Tools and Applications: 4th …, 2008
842008
FPGAs for software programmers
D Koch, F Hannig, D Ziener
822016
ExaStencils: Advanced stencil-code engineering
C Lengauer, S Apel, M Bolten, A Größlinger, F Hannig, H Köstler, U Rüde, ...
Euro-Par 2014: Parallel Processing Workshops: Euro-Par 2014 International …, 2014
762014
ExaSlang: A domain-specific language for highly scalable multigrid solvers
C Schmitt, S Kuckuk, F Hannig, H Köstler, J Teich
2014 Fourth international workshop on domain-specific languages and high …, 2014
682014
Generating device-specific GPU code for local operators in medical imaging
R Membarth, F Hannig, J Teich, M Körner, W Eckert
2012 IEEE 26th International Parallel and Distributed Processing Symposium …, 2012
662012
Power density-aware resource management for heterogeneous tiled multicores
H Khdr, S Pagani, E Sousa, V Lari, A Pathania, F Hannig, M Shafique, ...
IEEE Transactions on Computers 66 (3), 488-501, 2016
632016
Code generation from a domain-specific language for C-based HLS of hardware accelerators
O Reiche, M Schmid, F Hannig, R Membarth, J Teich
Proceedings of the 2014 International Conference on Hardware/Software …, 2014
582014
Resource-aware programming and simulation of MPSoC architectures through extension of X10
F Hannig, S Roloff, G Snelting, J Teich, A Zwinkau
Proceedings of the 14th International Workshop on Software and Compilers for …, 2011
532011
Programming abstractions for data locality
A Tate, A Kamil, A Dubey, A Groblinger, B Chamberlain, B Goglin, ...
Office of Scientific and Technical Information (OSTI), 2014
512014
Towards domain-specific computing for stencil codes in HPC
R Membarth, F Hannig, J Teich, H Köstler
2012 SC Companion: High Performance Computing, Networking Storage and …, 2012
442012
Decentralized dynamic resource management support for massively parallel processor arrays
V Lari, A Narovlyanskyy, F Hannig, J Teich
ASAP 2011-22nd IEEE International Conference on Application-specific Systems …, 2011
442011
Code generation for embedded heterogeneous architectures on Android
R Membarth, O Reiche, F Hannig, J Teich
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014
412014
Design space exploration for massively parallel processor arrays
F Hannig, J Teich
Parallel Computing Technologies: 6th International Conference, PaCT 2001 …, 2001
412001
Generating FPGA-based image processing accelerators with Hipacc
O Reiche, MA Özkan, R Membarth, J Teich, F Hannig
2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD …, 2017
402017
FPGA-based accelerator design from a domain-specific language
MA Özkan, O Reiche, F Hannig, J Teich
2016 26th International Conference on Field Programmable Logic and …, 2016
362016
A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template.
D Kissler, F Hannig, A Kupriyanov, J Teich
ReCoSoC, 31-37, 2006
362006
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