| Modular routing design for chiplet-based systems J Yin, Z Lin, O Kayiran, M Poremba, MSB Altaf, NE Jerger, GH Loh 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture …, 2018 | 130 | 2018 |
| Lost in abstraction: Pitfalls of analyzing GPUs at the intermediate language level A Gutierrez, BM Beckmann, A Dutu, J Gross, M LeBeane, J Kalamatianos, ... 2018 IEEE International Symposium on High Performance Computer Architecture …, 2018 | 96 | 2018 |
| Kite: A family of heterogeneous interposer topologies enabled via accurate interconnect modeling S Bharadwaj, J Yin, B Beckmann, T Krishna 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 68 | 2020 |
| Tenet: A framework for modeling tensor dataflow based on relation-centric notation L Lu, N Guan, Y Wang, L Jia, Z Luo, J Yin, J Cong, Y Liang 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture …, 2021 | 63 | 2021 |
| Designing a cost-effective cache replacement policy using machine learning S Sethumurugan, J Yin, J Sartori 2021 IEEE International Symposium on High-Performance Computer Architecture …, 2021 | 55 | 2021 |
| Energy-efficient time-division multiplexed hybrid-switched noc for heterogeneous multicore systems J Yin, P Zhou, SS Sapatnekar, A Zhai 2014 IEEE 28th international parallel and distributed processing symposium …, 2014 | 48 | 2014 |
| Toward more efficient noc arbitration: A deep reinforcement learning approach J Yin, Y Eckert, S Che, M Oskin, GH Loh Proc. IEEE 1st Int. Workshop AI-assisted Des. Architecture 128, 2018 | 34 | 2018 |
| Experiences with ml-driven design: A noc case study J Yin, S Sethumurugan, Y Eckert, C Patel, A Smith, E Morton, M Oskin, ... 2020 IEEE International Symposium on High Performance Computer Architecture …, 2020 | 32 | 2020 |
| There and back again: Optimizing the interconnect in networks of memory cubes M Poremba, I Akgun, J Yin, O Kayiran, Y Xie, GH Loh ACM SIGARCH Computer Architecture News 45 (2), 678-690, 2017 | 29 | 2017 |
| Energy-efficient non-minimal path on-chip interconnection network for heterogeneous systems J Yin, P Zhou, A Holey, SS Sapatnekar, A Zhai Proceedings of the 2012 ACM/IEEE international symposium on Low power …, 2012 | 28 | 2012 |
| NoC frequency scaling with flexible-pipeline routers P Zhou, J Yin, A Zhai, SS Sapatnekar IEEE/ACM International Symposium on Low Power Electronics and Design, 403-408, 2011 | 25 | 2011 |
| CryptoGCN: Fast and scalable homomorphically encrypted graph convolutional network inference R Ran, W Wang, Q Gang, J Yin, N Xu, W Wen Advances in Neural information processing systems 35, 37676-37689, 2022 | 19 | 2022 |
| Improving address translation in multi-gpus via sharing and spilling aware tlb design B Li, J Yin, Y Zhang, X Tang MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture …, 2021 | 19 | 2021 |
| Efficient synthetic traffic models for large, complex SoCs J Yin, O Kayiran, M Poremba, NE Jerger, GH Loh 2016 IEEE International Symposium on High Performance Computer Architecture …, 2016 | 17 | 2016 |
| {NeuroPots}: Realtime Proactive Defense against {Bit-Flip} Attacks in Neural Networks Q Liu, J Yin, W Wen, C Yang, S Sha 32nd USENIX Security Symposium (USENIX Security 23), 6347-6364, 2023 | 11 | 2023 |
| Design challenges of intra-and inter-chiplet interconnection C Chen, J Yin, Y Peng, M Palesi, W Cao, L Huang, AK Singh, H Zhi, ... IEEE Design and Test 39 (6), 99-109, 2022 | 11 | 2022 |
| Modular Routing Design for Chiplet-Based Systems. In 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA). 726–738 J Yin, Z Lin, O Kayiran, M Poremba, MSB Altaf, NE Jerger, GH Loh | 10 | 2018 |
| Trans-fw: Short circuiting page table walk in multi-gpu systems via remote forwarding B Li, J Yin, A Holey, Y Zhang, J Yang, X Tang 2023 IEEE International Symposium on High-Performance Computer Architecture …, 2023 | 9 | 2023 |
| Selecting a precision level for executing a workload in an electronic device AT Gutierrez, S Blagodurov, SA Moe, X Zhang, J Yin, MD Sinclair US Patent 11,150,899, 2021 | 7 | 2021 |
| Rubick: A synthesis framework for spatial architectures via dataflow decomposition Z Luo, L Lu, S Zheng, J Yin, J Cong, J Yin, Y Liang 2023 60th ACM/IEEE Design Automation Conference (DAC), 1-6, 2023 | 6 | 2023 |
Matthew PorembaAMD ResearchVerified email at amd.com
