Dr. Hardik Shah
Dr. Hardik Shah
Research Assistant, Technical University Munich, fortiss GmbH
Verified email at in.tum.de
Title
Cited by
Cited by
Year
Bounding WCET of applications using SDRAM with priority based budget scheduling in MPSoCs
H Shah, A Raabe, A Knoll
2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 665-670, 2012
402012
Priority division: A high-speed shared-memory bus arbitration with bounded latency
H Shah, A Raabe, A Knoll
2011 Design, Automation & Test in Europe, 1-4, 2011
342011
Bounding SDRAM interference: Detailed analysis vs. latency-rate analysis
H Shah, A Knoll, B Akesson
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 308-313, 2013
252013
Timing Anomalies in Multi-core Architectures due to the Interference on the Shared Resources
H Shah, K Huang, A Knoll
Design Automation Conference (ASP-DAC), 2014 19th Asia and South Pacific …, 2014
182014
Measurement based WCET analysis for multi-core architectures
H Shah, A Coombes, A Raabe, K Huang, A Knoll
Proceedings of the 22Nd International Conference on Real-Time Networks and …, 2014
142014
Challenges of wcet analysis in cots multi-core due to different levels of abstraction
H Shah, A Raabe, A Knoll
hiRES 2013, 2013
122013
The priority division arbiter for low wcet and high resource utilization in multi-core architectures
H Shah, K Huang, A Knoll
Proceedings of the 22nd International Conference on Real-Time Networks and …, 2014
42014
Implementation of high speed low power combinational and sequential circuits using reversible logic
H Shah, A Rao, M Deshpande, A Rane, S Nagvekar
2014 International Conference on Advances in Electrical Engineering (ICAEE), 1-4, 2014
32014
Weighted execution time analysis of applications on cots multi-core architectures
H Shah, K Huang, A Knoll
32013
A lego/fpga-based platform for the education of cyber-physical/embedded systems
K Huang, H Shah, K Savant, D Chen, G Chen, S Klose, A Knoll
Workshop on Embedded and Cyber-Physical Systems Education (WESE), 2013
22013
Chinesisch-Deutsches Netzwerk zur Elektromobilität, Teilprojekt: Car2X Integration in Automotive Elektrik/Elektronik Architekturen: Laufzeit des Vorhabens: 01.03. 2012-28.02 …
K Huang, H Shah, A Knoll
Lehrstuhl für Echtzeitsysteme und Robotik, Technische Universität München, 2016
2016
Netzwerk TU9/CN Elektromobilität-Teilvorhaben: Innovative Electronic Control Units (ECU) für Elektrofahrzeuge
K Huang, H Shah, A Knoll
Technische Universität München, Department of Robotics and Embedded Systems, 2015
2015
Predictable and high performance multi-core architectures
H Shah
Technische Universität München, 2015
2015
Dynamic Priority Queue: An SDRAM Arbiter With Bounded Access Latencies for Tight WCET Calculation
H Shah, A Raabe, A Knoll
arXiv preprint arXiv:1207.1187, 2012
2012
Mehrkernsysteme für safety-kritische Echtzeitsysteme
A Raabe, H Shah, A Hattendorf
Embedded Software Engineering Kongress, 2012
2012
A study of accidents on NH No 8 of Ahmedabad Ajmer section from Kms 388/4 to 481/4 (93Kms)
VP Kamdar, MD Deshpande, HK Bhatt, HJ Shah
Indian Highways 16 (12), 1988
1988
Design of High Speed 32-bit Microarchitecture for Emulation of Quantum Computing Algorithms
M Deshpande, H Shah, V Kini, C Bafna
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Articles 1–17