Follow
Ryan Keech
Ryan Keech
MIT Lincoln Laboratory
Verified email at ll.mit.edu
Title
Cited by
Cited by
Year
Scaling effects in perovskite ferroelectrics: fundamental limits and process‐structure‐property relations
JF Ihlefeld, DT Harris, R Keech, JL Jones, JP Maria, S Trolier‐McKinstry
Journal of the American Ceramic Society 99 (8), 2537-2557, 2016
2002016
3-D self-aligned stacked NMOS-on-PMOS nanoribbon transistors for continued Moore’s law scaling
CY Huang, G Dewey, E Mannebach, A Phan, P Morrow, W Rachmady, ...
2020 IEEE International Electron Devices Meeting (IEDM), 20.6. 1-20.6. 4, 2020
712020
Lateral scaling of Pb (Mg1/3Nb2/3) O3-PbTiO3 thin films for piezoelectric logic applications
R Keech, S Shetty, MA Kuroda, X Hu Liu, GJ Martyna, DM Newns, ...
Journal of Applied Physics 115 (23), 2014
432014
Declamped piezoelectric coefficients in patterned 70/30 lead magnesium niobate–lead titanate thin films
R Keech, L Ye, JL Bosse, G Esteves, J Guerrier, JL Jones, MA Kuroda, ...
Advanced Functional Materials 27 (9), 1605014, 2017
362017
Pathway to the piezoelectronic transduction logic device
PM Solomon, BA Bryce, MA Kuroda, R Keech, S Shetty, TM Shaw, ...
Nano letters 15 (4), 2391-2395, 2015
332015
Thickness‐dependent domain wall reorientation in 70/30 lead magnesium niobate‐lead titanate thin films
R Keech, C Morandi, M Wallace, G Esteves, L Denis, J Guerrier, ...
Journal of the American Ceramic Society 100 (9), 3961-3972, 2017
142017
Management of lead content for growth of {001}‐oriented lead magnesium niobate‐lead titanate thin films
R Keech, S Shetty, K Wang, S Trolier‐McKinstry
Journal of the American Ceramic Society 99 (4), 1144-1146, 2016
132016
Arsenic-doped epitaxial, source/drain regions for NMOS
A Murthy, R Keech, NG Minutillo, R Jhaveri
US Patent 11,610,889, 2023
112023
Source or drain structures with phosphorous and arsenic co-dopants
A Murthy, R Keech, NG Minutillo, S Vishwanath
US Patent 11,552,169, 2023
112023
Contact resistance reduction in transistor devices with metallization on both sides
K Ganguly, R Keech, S Rafique, GA Glass, AS Murthy, E Mannebach, ...
US Patent App. 16/911,771, 2021
112021
The PiezoElectronic switch: A path to low energy electronics
PM Solomon, B Bryce, R Keech, TM Shaw, M Copel, LW Hung, A Schrott, ...
2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S), 1-2, 2013
72013
Source or drain structures for germanium n-channel devices
R Keech, B Chu-Kung, S Rafique, D Merrill, A Agrawal, H Kennel, Y Cao, ...
US Patent App. 16/368,088, 2020
42020
Dimensional Scaling of Perovskite Ferroelectric Thin Films
RR Keech
42016
Source or drain structures with vertical trenches
R Keech, N Minutillo, A Murthy, A Budrevich, P Wells
US Patent 11,935,887, 2024
32024
Gate-all-around integrated circuit structures having strained source or drain structures on insulator
A Agrawal, AS Murthy, C Bomberger, JT Kavalieros, K Ganguly, R Keech, ...
US Patent App. 16/912,127, 2021
22021
Three-dimensional integrated circuits (3DICs) including upper-level transistors with epitaxial source and drain material
A Agrawal, G Dewey, CY Huang, W Rachmady, A Murthy, R Keech, ...
US Patent 11,164,785, 2021
22021
Top gate recessed channel CMOS thin film transistor in the back end of line and methods of fabrication
G Dewey, R Keech, C Bomberger, CY Huang, A Agrawal, W Rachmady, ...
US Patent 11,328,988, 2022
12022
Gate-all-around integrated circuit structures having strained source or drain structures on gate dielectric layer
A Agrawal, AS Murthy, JT Kavalieros, K Ganguly, R Keech, S Chouksey, ...
US Patent App. 16/912,136, 2021
12021
Gate-all-around integrated circuit structures having strained dual nanoribbon channel structures
A Agrawal, B Mueller, JT Kavalieros, J Torres, K Jun, S Chouksey, ...
US Patent App. 16/913,333, 2021
12021
TOP GATE RECESSED CHANNEL CMOS THIN FILM TRANSISTOR AND METHODS OF FABRICATION
G Dewey, R Keech, C Bomberger, C Huang, A Agrawal, W Rachmady, ...
US Patent App. 18/395,192, 2024
2024
The system can't perform the operation now. Try again later.
Articles 1–20