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Hiroki Nakahara
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BRein memory: A single-chip binary/ternary reconfigurable in-memory deep neural network accelerator achieving 1.4 TOPS at 0.6 W
K Ando, K Ueyoshi, K Orimo, H Yonekawa, S Sato, H Nakahara, ...
IEEE Journal of Solid-State Circuits 53 (4), 983-994, 2017
1812017
A lightweight YOLOv2: A binarized CNN with a parallel support vector regression for an FPGA
H Nakahara, H Yonekawa, T Fujii, S Sato
Proceedings of the 2018 ACM/SIGDA International Symposium on field …, 2018
1622018
A fully connected layer elimination for a binarizec convolutional neural network on an FPGA
H Nakahara, T Fujii, S Sato
2017 27th international conference on field programmable logic and …, 2017
1212017
On-chip memory based binarized convolutional deep neural network applying batch normalization free technique on an FPGA
H Yonekawa, H Nakahara
2017 IEEE international parallel and distributed processing symposium …, 2017
1092017
BRein memory: A 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS
K Ando, K Ueyoshi, K Orimo, H Yonekawa, S Sato, H Nakahara, M Ikebe, ...
2017 Symposium on VLSI Circuits, C24-C25, 2017
962017
A deep convolutional neural network based on nested residue number system
H Nakahara, T Sasao
2015 25th International Conference on Field Programmable Logic and …, 2015
802015
Principles and structures of FPGAs
H Amano
702018
A memory-based realization of a binarized deep convolutional neural network
H Nakahara, H Yonekawa, T Sasao, H Iwamoto, M Motomura
2016 International Conference on Field-Programmable Technology (FPT), 277-280, 2016
542016
A random forest using a multi-valued decision diagram on an FPGA
H Nakahara, A Jinguji, S Sato, T Sasao
2017 IEEE 47th international symposium on multiple-valued logic (ISMVL), 266-271, 2017
432017
A High-speed Low-power Deep Neural Network on an FPGA based on the Nested RNS: Applied to an Object Detector
H Nakahara, T Sasao
2018 IEEE international symposium on circuits and systems (ISCAS), 1-5, 2018
402018
An object detector based on multiscale sliding window search using a fully pipelined binarized CNN on an FPGA
H Nakahara, H Yonekawa, S Sato
2017 international conference on field programmable technology (ICFPT), 168-175, 2017
382017
A regular expression matching circuit based on a decomposed automaton
H Nakahara, T Sasao, M Matsuura
Reconfigurable Computing: Architectures, Tools and Applications: 7th …, 2011
372011
High-throughput convolutional neural network on an FPGA by customized JPEG compression
H Nakahara, Z Que, W Luk
2020 IEEE 28th Annual International Symposium on Field-Programmable Custom …, 2020
362020
Optimizing reconfigurable recurrent neural networks
Z Que, H Nakahara, E Nurvitadhi, H Fan, C Zeng, J Meng, X Niu, W Luk
2020 IEEE 28th Annual International Symposium on Field-Programmable Custom …, 2020
302020
New generation dynamically reconfigurable processor technology for accelerating embedded AI applications
T Fujii, T Toi, T Tanaka, K Togawa, T Kitaoka, K Nishino, N Nakamura, ...
2018 IEEE symposium on VLSI circuits, 41-42, 2018
272018
A demonstration of FPGA-based you only look once version2 (YOLOv2)
H Nakahara, M Shimoda, S Sato
2018 28th International Conference on Field Programmable Logic and …, 2018
262018
All binarized convolutional neural network and its implementation on an FPGA
M Shimoda, S Sato, H Nakahara
2017 International Conference on Field Programmable Technology (ICFPT), 291-294, 2017
262017
FPGA-based training accelerator utilizing sparseness of convolutional neural network
H Nakahara, Y Sada, M Shimoda, K Sayama, A Jinguji, S Sato
2019 29th International Conference on Field Programmable Logic and …, 2019
242019
A regular expression matching circuit based on a modular non-deterministic finite automaton with multi-character transition
H Nakahara, T Sasao, M Matsuura
Proc. 16th Workshop on Synthesis And System Integration of Mixed Information …, 2010
242010
GUINNESS: A GUI based binarized deep neural network framework for software programmers
H Nakahara, H Yonekawa, T Fujii, M Shimoda, S Sato
IEICE TRANSACTIONS on Information and Systems 102 (5), 1003-1011, 2019
212019
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