| Statistical timing analysis considering spatial correlations using a single PERT-like traversal H Chang, SS Sapatnekar ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No …, 2003 | 696 | 2003 |
| Thermal via placement in 3D ICs B Goplen, S Sapatnekar Proceedings of the 2005 international symposium on Physical design, 167-174, 2005 | 439 | 2005 |
| Hierarchical analysis of power distribution networks M Zhao, RV Panda, SS Sapatnekar, T Edwards, R Chaudhry, D Blaauw Proceedings of the 37th Annual Design Automation Conference, 150-155, 2000 | 439 | 2000 |
| Impact of NBTI on SRAM read stability and design for reliability SV Kumar, KH Kim, SS Sapatnekar 7th International Symposium on Quality Electronic Design (ISQED'06), 6 pp.-218, 2006 | 394 | 2006 |
| An exact solution to the transistor sizing problem for CMOS circuits using convex optimization SS Sapatnekar, VB Rao, PM Vaidya, SM Kang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1993 | 377 | 1993 |
| Efficient thermal placement of standard cells in 3D ICs using a force directed approach B Goplen, S Sapatnekar ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No …, 2003 | 348 | 2003 |
| Statistical timing analysis under spatial correlations H Chang, SS Sapatnekar IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2005 | 345 | 2005 |
| Handbook of algorithms for physical design automation CJ Alpert, DP Mehta, SS Sapatnekar CRC press, 2008 | 330 | 2008 |
| Full-chip analysis of leakage power under process variations, including spatial correlations H Chang, SS Sapatnekar Proceedings of the 42nd Annual Design Automation Conference, 523-528, 2005 | 289 | 2005 |
| NBTI-aware synthesis of digital circuits SV Kumar, CH Kim, SS Sapatnekar Proceedings of the 44th annual Design Automation Conference, 370-375, 2007 | 275 | 2007 |
| An analytical model for negative bias temperature instability SV Kumar, CH Kim, SS Sapatnekar Proceedings of the 2006 IEEE/ACM international conference on Computer-aided …, 2006 | 270 | 2006 |
| Timing S Sapatnekar Springer, 2004 | 233 | 2004 |
| A graph-theoretic approach to clock skew optimization RB Deokar, SS Sapatnekar 1994 IEEE International Symposium on Circuits and Systems (ISCAS) 1, 407-410, 1994 | 232 | 1994 |
| Random walks in a supply network H Qian, SR Nassif, SS Sapatnekar Proceedings of the 40th annual Design Automation Conference, 93-98, 2003 | 211 | 2003 |
| Placement and routing in 3D integrated circuits C Ababei, Y Feng, B Goplen, H Mogal, T Zhang, K Bazargan, ... IEEE Design & Test of Computers 22 (6), 520-531, 2005 | 210 | 2005 |
| Power grid analysis using random walks H Qian, SR Nassif, SS Sapatnekar IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2005 | 208 | 2005 |
| Spin-based computing: Device concepts, current status, and a case study on a high-performance microprocessor J Kim, A Paul, PA Crowell, SJ Koester, SS Sapatnekar, JP Wang, CH Kim Proceedings of the IEEE 103 (1), 106-130, 2014 | 177 | 2014 |
| Placement of thermal vias in 3-D ICs using various thermal objectives B Goplen, SS Sapatnekar IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006 | 177 | 2006 |
| Optimal decoupling capacitor sizing and placement for standard-cell layout designs H Su, SS Sapatnekar, SR Nassif Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions …, 2003 | 165 | 2003 |
| A framework for exploiting task and data parallelism on distributed memory multicomputers S Ramaswamy, S Sapatnekar, P Banerjee IEEE transactions on parallel and distributed systems 8 (11), 1098-1116, 1997 | 161 | 1997 |
