Aneesh Nainani
Aneesh Nainani
Stanford Univeristy, Applied Materials
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Zitiert von
Zitiert von
Increase in current density for metal contacts to n-germanium by inserting interfacial layer to reduce Schottky barrier height
JYJ Lin, AM Roy, A Nainani, Y Sun, KC Saraswat
Applied Physics Letters 98 (9), 092113, 2011
GeSn technology: Extending the Ge electronics roadmap
2011 International Electron Devices Meeting, 16.6. 1-16.6. 4, 2011
Fermi-level unpinning and low resistivity in contacts to n-type Ge with a thin ZnO interfacial layer
P Paramahans Manik, R Kesh Mishra, V Pavan Kishore, P Ray, A Nainani, ...
Applied Physics Letters 101 (18), 182105, 2012
Optimization of the Interface and a High-Mobility GaSb pMOSFET
A Nainani, T Irisawa, Z Yuan, BR Bennett, JB Boos, Y Nishi, KC Saraswat
IEEE Transactions on Electron Devices 58 (10), 3407-3415, 2011
High-mobility Ge N-MOSFETs and mobility degradation mechanisms
D Kuzum, T Krishnamohan, A Nainani, Y Sun, PA Pianetta, HSP Wong, ...
IEEE transactions on electron devices 58 (1), 59-66, 2010
Contact resistivity reduction through interfacial layer doping in metal-interfacial layer-semiconductor contacts
S Gupta, P Paramahans Manik, R Kesh Mishra, A Nainani, MC Abraham, ...
Journal of Applied Physics 113 (23), 234505, 2013
Experimental demonstration of high mobility Ge NMOS
D Kuzum, T Krishnamohan, A Nainani, Y Sun, PA Pianetta, KC Saraswat
2009 IEEE International Electron Devices Meeting (IEDM), 1-4, 2009
Device quality Sb-based compound semiconductor surface: A comparative study of chemical cleaning
A Nainani, Y Sun, T Irisawa, Z Yuan, M Kobayashi, P Pianetta, BR Bennett, ...
Journal of Applied Physics 109 (11), 114908, 2011
InxGa1-xSb channel p-metal-oxide-semiconductor field effect transistors: Effect of strain and heterostructure design
A Nainani, Z Yuan, T Krishnamohan, BR Bennett, JB Boos, M Reason, ...
Journal of Applied Physics 110 (1), 014503, 2011
Impact of fixed charge on metal-insulator-semiconductor barrier height reduction
J Hu, A Nainani, Y Sun, KC Saraswat, HS Philip Wong
Applied Physics Letters 99 (25), 252104, 2011
Schottky barrier height reduction for metal/n-GaSb contact by inserting interfacial layer with low tunneling resistance
Z Yuan, A Nainani, Y Sun, JYJ Lin, P Pianetta, KC Saraswat
Applied Physics Letters 98 (17), 172106, 2011
Fluorine passivation of vacancy defects in bulk germanium for Ge metal-oxide-semiconductor field-effect transistor application
WS Jung, JH Park, A Nainani, D Nam, KC Saraswat
Applied Physics Letters 101 (7), 072104, 2012
High performance germanium n-MOSFET with antimony dopant activation beyond 1×1020cm−3
G Thareja, J Liang, S Chopra, B Adams, N Patil, SL Cheng, A Nainani, ...
2010 International Electron Devices Meeting, 10.5. 1-10.5. 4, 2010
Development of high-k dielectric for antimonides and a sub 350° C III–V pMOSFET outperforming germanium
A Nainani, T Irisawa, Z Yuan, Y Sun, T Krishnamohan, M Reason, ...
2010 International Electron Devices Meeting, 6.4. 1-6.4. 4, 2010
Germanium oxynitride gate interlayer dielectric formed on Ge (100) using decoupled plasma nitridation
P Bhatt, K Chaudhuri, S Kothari, A Nainani, S Lodha
Applied Physics Letters 103 (17), 172107, 2013
Enhancing hole mobility in III-V semiconductors
A Nainani, BR Bennett, J Brad Boos, MG Ancona, KC Saraswat
Journal of Applied Physics 111 (10), 103706, 2012
Antimonide-based heterostructure p-channel MOSFETs with Ni-alloy source/drain
Z Yuan, A Kumar, CY Chen, A Nainani, BR Bennett, JB Boos, ...
IEEE electron device letters 34 (11), 1367-1369, 2013
Electron Devices Meeting (IEDM), 2011 IEEE International
S Gupta, R Chen, B Magyari-Kope, H Lin, B Yang, A Nainani, Y Nishi, ...
IEEE, 2011
High Performance 400 °C p+/n Ge Junctions Using Cryogenic Boron Implantation
P Bhatt, P Swarnkar, F Basheer, C Hatem, A Nainani, S Lodha
IEEE electron device letters 35 (7), 717-719, 2014
InGaSb: Single channel solution for realizing III–V CMOS
Z Yuan, A Nainani, A Kumar, X Guan, BR Bennett, JB Boos, MG Ancona, ...
2012 Symposium on VLSI Technology (VLSIT), 185-186, 2012
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