| Design of 56 Gb/s NRZ and PAM4 SerDes transceivers in CMOS technologies J Lee, PC Chiang, PJ Peng, LY Chen, CC Weng IEEE Journal of Solid-State Circuits 50 (9), 2061-2073, 2015 | 157 | 2015 |
| 100Gb/s Ethernet chipsets in 65nm CMOS technology JY Jiang, PC Chiang, HW Hung, CL Lin, T Yoon, J Lee 2013 IEEE International Solid-State Circuits Conference Digest of Technical …, 2013 | 77 | 2013 |
| 2.3 60Gb/s NRZ and PAM4 transmitters for 400GbE in 65nm CMOS PC Chiang, HW Hung, HY Chu, GS Chen, J Lee 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 54 | 2014 |
| 4× 25 Gb/s transceiver with optical front-end for 100 GbE system in 65 nm CMOS technology PC Chiang, JY Jiang, HW Hung, CY Wu, GS Chen, J Lee IEEE Journal of Solid-State Circuits 50 (2), 573-585, 2014 | 50 | 2014 |
| Design of a 50-Gb/s hybrid integrated Si-photonic optical link in 16-nm FinFET M Raj, Y Frans, PC Chiang, SLC Ambatipudi, D Mahashin, P De Heyn, ... IEEE Journal of Solid-State Circuits 55 (4), 1086-1095, 2020 | 43 | 2020 |
| A 126mW 56Gb/s NRZ wireline transceiver for synchronous short-reach applications in 16nm FinFET M Erett, D Carey, J Hudner, R Casey, K Geary, P Neto, M Raj, S McLeod, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 274-276, 2018 | 42 | 2018 |
| A 32.75-Gb/s voltage-mode transmitter with three-tap FFE in 16-nm CMOS KL Chan, KH Tan, Y Frans, J Im, P Upadhyaya, SW Lim, A Roldan, ... IEEE Journal of Solid-State Circuits 52 (10), 2663-2678, 2017 | 42 | 2017 |
| A 112-Gb/s PAM4 transmitter in 16nm FinFET KH Tan, PC Chiang, Y Wang, H Zhao, A Roldan, H Zhao, N Narang, ... 2018 IEEE Symposium on VLSI Circuits, 45-46, 2018 | 32 | 2018 |
| 56Gb/s PAM4 and NRZ SerDes transceivers in 40nm CMOS J Lee, PC Chiang, CC Weng 2015 Symposium on VLSI Circuits (VLSI Circuits), C118-C119, 2015 | 23 | 2015 |
| Quadrature clock correction circuit for transmitters HB Zhao, KH Tan, PC Chiang, Y Frans US Patent 10,680,592, 2020 | 13 | 2020 |
| 50Gb/s Hybrid Integrated Si-Photonic Optical Link in 16nm FinFET M Raj, Y Frans, PC Chiang, SLC Ambatipudi, D Mahashin, P De Heyn, ... 2020 European Conference on Optical Communications (ECOC), 1-4, 2020 | 8 | 2020 |
| A 2.25 pJ/bit Multi-lane Transceiver for Short Reach Intra-package and Inter-package Communication in 16nm FinFET M Erett, D Carey, R Casey, J Hudner, K Geary, T Lee, M Raj, H Zhang, ... 2019 IEEE Custom Integrated Circuits Conference (CICC), 1-8, 2019 | 7 | 2019 |
| Clock phase aligner for high speed data serializers PC Chiang, KH Tan, AB Roldan, N Narang, Y Wang, Y Frans, KY Chang US Patent 10,712,770, 2020 | 4 | 2020 |
| Temperature-locked loop for optical elements having a temperature-dependent response PC Chiang, M Raj, C Xie, SY Chen, S Kumar, S Pattanagiri, P Upadhyaya, ... US Patent 11,005,572, 2021 | 2 | 2021 |
| Thermal calibration of a ring modulator PC Chiang, KH Tan, G Modi, N Narang, Z Haibing, Y Frans US Patent 10,651,933, 2020 | 2 | 2020 |
| A low-power CMOS LNA using noise suppression and distortion cancellation techniques with inductive bandwidth extension CF Li, CM Lai, PC Chiang, PC Huang 2011 International SoC Design Conference, 120-123, 2011 | 2 | 2011 |
| Digital-to-analog converter (DAC)-based driver for optical modulators HB Zhao, KH Tan, PC Chiang, Y Wang, Y Frans US Patent 10,598,852, 2020 | 1 | 2020 |
Mayank RajSr. Design Manager, XILINX Inc.Verified email at caltech.edu
