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Ashish Pal
Ashish Pal
Device & Process Simulation Engineer, Applied Materials
Bestätigte E-Mail-Adresse bei amat.com - Startseite
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Zitiert von
Zitiert von
Jahr
Monolithic 3D integration of logic and memory: Carbon nanotube FETs, resistive RAM, and silicon FETs
MM Shulaker, TF Wu, A Pal, L Zhao, Y Nishi, K Saraswat, HSP Wong, ...
2014 IEEE International Electron Devices Meeting, 27.4. 1-27.4. 4, 2014
1872014
Enhancing ferroelectricity in dopant-free hafnium oxide
A Pal, VK Narasimhan, S Weeks, K Littau, D Pramanik, T Chiang
Applied Physics Letters 110 (2), 2017
1862017
Insights into the design and optimization of tunnel-FET devices and circuits
A Pal, AB Sachid, H Gossner, VR Rao
IEEE Transactions on Electron devices 58 (4), 1045-1053, 2011
1332011
Engineering of Ferroelectric HfO2–ZrO2 Nanolaminates
SL Weeks, A Pal, VK Narasimhan, KA Littau, T Chiang
ACS Applied Materials & Interfaces 9 (15), 13440-13447, 2017
912017
Semiconductor devices
H Gossner, R Rao, A Sachid, A Pal, R Asra
US Patent 8,405,121, 2013
822013
ISFET pH sensitivity: counter-ions play a key role
KB Parizi, X Xu, A Pal, X Hu, HSP Wong
Scientific reports 7 (1), 41305, 2017
762017
Crystal Phase Distribution and Ferroelectricity in Ultrathin HfO2–ZrO2 Bilayers
ME McBriarty, VK Narasimhan, SL Weeks, A Pal, H Fang, TA Petach, ...
physica status solidi (b) 257 (1), 1900285, 2020
242020
Performance Improvement of One-Transistor DRAM by Band Engineering
A Pal, A Nainani, S Gupta, KC Saraswat
Electron Device Letters, IEEE, 1-3, 2012
212012
Impact of MOL/BEOL air-spacer on parasitic capacitance and circuit performance at 3 nm node
A Pal, S Mittal, EM Bazizi, A Sachid, M Saremi, B Colombeau, G Thareja, ...
2019 International Conference on Simulation of Semiconductor Processes and …, 2019
142019
Materials to systems co-optimization platform for rapid technology development targeting future generation CMOS nodes
EM Bazizi, A Pal, J Kim, L Jiang, V Reddy, B Alexander, ...
IEEE Transactions on Electron Devices 68 (11), 5358-5363, 2021
112021
Complementary FET device and circuit level evaluation using fin-based and sheet-based configurations targeting 3nm node and beyond
L Jiang, A Pal, EM Bazizi, M Saremi, H Ren, B Alexander, ...
2020 International Conference on Simulation of Semiconductor Processes and …, 2020
102020
Transistor-based apparatuses, systems and methods
A Pal, A Nainani, KC Saraswat
US Patent 8,969,924, 2015
102015
Reduction of surface roughness in epitaxially grown germanium by controlled thermal oxidation
WS Jung, JH Nam, A Pal, JH Lee, Y Na, Y Kim, JH Lee, KC Saraswat
IEEE Electron Device Letters 36 (4), 297-299, 2015
92015
Estrogenic activity of tree leaves as animal feed.
BN Ray, AK Pal
Indian Journal of Physiology and Allied Sciences 20, 6-10, 1966
81966
Using modified Mach-Zehnder interferometer to get better nonlinear correction term of an isotropic nonlinear material
A Pal, S Mukhopadhyay
Chinese Optics Letters 7 (7), 624-626, 2009
72009
Airgap formation processes
A Pal, G Thareja, S Lin, CM Hsu, NK Ingle, A Bhatnagar, A Wang
US Patent 11,211,286, 2021
62021
Electrical characterization of GaP-Silicon interface for memory and transistor applications
A Pal, A Nainani, Z Ye, X Bao, E Sanchez, KC Saraswat
IEEE transactions on electron devices 60 (7), 2238-2245, 2013
62013
H.. P. Wong, and S. Mitra. Monolithic 3D integration of logic and memory: Carbon nanotube FETs, resistive RAM, and silicon FETs
MM Shulaker, TF Wu, A Pal, L Zhao, Y Nishi, K Saraswat
Proc. Int. Electron Devices Meeting, pages 27, 1-27.4, 0
6
Semiconductor devices
H Gossner, R Rao, A Sachid, A Pal, R Asra
US Patent 8,878,234, 2014
52014
Embalming with formalin–benefits and pitfalls
AK Pal, UP Bhanarkar, B Ray
Sch Int J Anat Physiol 5 (3), 70-77, 2022
42022
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