Jiang Hu
Jiang Hu
Professor of Electrical and Computer Engineering, Texas A&M University
Bestätigte E-Mail-Adresse bei tamu.edu - Startseite
Titel
Zitiert von
Zitiert von
Jahr
Handbook of algorithms for physical design automation
CJ Alpert, DP Mehta, SS Sapatnekar
CRC press, 2008
2832008
A practical methodology for early buffer and wire resource allocation
CJ Alpert, J Hu, SS Sapatnekar, PG Villarrubia
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2003
1932003
A timing-constrained simultaneous global routing algorithm
J Hu, SS Sapatnekar
IEEE Transactions on computer-aided design of integrated circuits and …, 2002
156*2002
Reducing clock skew variability via crosslinks
A Rajaram, J Hu, R Mahapatra
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006
1412006
Porosity-aware buffered Steiner tree construction
CJ Alpert, G Gandham, M Hrkic, J Hu, ST Quay, CN Sze
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2004
1412004
Steiner tree optimization for buffers, blockages, and bays
CJ Alpert, G Gandham, J Hu, JI Neves, ST Quay, SS Sapatnekar
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2001
139*2001
A survey on multi-net global routing for integrated circuits
J Hu, SS Sapatnekar
Integration 31 (1), 1-49, 2001
1182001
Joint precision optimization and high level synthesis for approximate computing
C Li, W Luo, SS Sapatnekar, J Hu
Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015
1062015
A new algorithm for simultaneous gate sizing and threshold voltage assignment
Y Liu, J Hu
IEEE Transactions on Computer-aided design of integrated circuits and …, 2010
1002010
Fast algorithms for slew-constrained minimum cost buffering
S Hu, CJ Alpert, J Hu, SK Karandikar, Z Li, W Shi, CN Sze
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2007
952007
An efficient merging scheme for prescribed skew clock routing
R Chaturvedi, J Hu
IEEE transactions on very large scale integration (VLSI) systems 13 (6), 750-754, 2005
91*2005
Buffered Steiner trees for difficult instances
CJ Alpert, M Hrkić, J Hu, AB Kahng, J Lillis, B Liu, ST Quay, ...
Proceedings of the 2001 international symposium on Physical design, 4-9, 2001
902001
Gate sizing for cell-library-based designs
S Hu, M Ketkar, J Hu
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2009
872009
Standard cell characterization considering lithography induced variations
K Cao, S Dobre, J Hu
2006 43rd ACM/IEEE Design Automation Conference, 801-804, 2006
862006
The cat and mouse in split manufacturing
Y Wang, P Chen, J Hu, G Li, J Rajendran
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (5), 805-817, 2018
792018
Algorithms for gate sizing and device parameter selection for high-performance designs
MM Ozdal, S Burns, J Hu
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012
78*2012
Combinatorial algorithms for fast clock mesh optimization
G Venkataraman, Z Feng, J Hu, P Li
IEEE transactions on very large scale integration (VLSI) systems 18 (1), 131-141, 2009
772009
In-network monitoring and control policy for DVFS of CMP networks-on-chip and last level caches
X Chen, Z Xu, H Kim, P Gratz, J Hu, M Kishinevsky, U Ogras
ACM Transactions on Design Automation of Electronic Systems (TODAES) 18 (4 …, 2013
752013
Dynamic voltage and frequency scaling for shared resources in multicore processor designs
X Chen, Z Xu, H Kim, PV Gratz, J Hu, M Kishinevsky, U Ogras, R Ayoub
2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC), 1-7, 2013
702013
Practical techniques to reduce skew and its variations in buffered clock networks
G Venkataraman, N Jayakumar, J Hu, P Li, S Khatri, A Rajaram, ...
ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005 …, 2005
662005
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