Yasuhiko Nakashima (中島康彦)
Yasuhiko Nakashima (中島康彦)
Professor of Computer Science, Nara Institute of Science and Technology
Verified email at - Homepage
Cited by
Cited by
A secure remote healthcare system for hospital using blockchain smart contract
HL Pham, TH Tran, Y Nakashima
2018 IEEE globecom workshops (GC Wkshps), 1-6, 2018
A high-speed dynamic instruction scheduling scheme for superscalar processors
M Goshima, K Nishino, Y Nakashima, S Mori, T Kitamura, S Tomita
Micro 34, 225-236, 2001
An efficient conversion of quantum circuits to a linear nearest neighbor architecture
Y Hirata
Nara Institute of Science and Technology, 2009
Data processing device for implementing instruction reuse, and digital data storage medium for storing a data processing program for implementing instruction reuse
Y Nakashima
US Patent 8,055,885, 2011
An efficient method to convert arbitrary quantum circuits to ones on a linear nearest neighbor architecture
Y Hirata, M Nakanishi, S Yamashita, Y Nakashima
2009 Third International Conference on Quantum, Nano and Micro Technologies …, 2009
A cgra-based approach for accelerating convolutional neural networks
M Tanomoto, S Takamaeda-Yamazaki, J Yao, Y Nakashima
2015 IEEE 9th International Symposium on Embedded Multicore/Many-core …, 2015
Design and evaluation of an auto-memoization processor.
T Tsumura, I Suzuki, Y Ikeuchi, H Matsuo, H Nakashima, Y Nakashima
Parallel and Distributed Computing and Networks, 230-235, 2007
Method and apparatus for negotiating bearer control parameters using property sets
SYC Scoggins, MM Watson
US Patent 7,826,384, 2010
Double SHA-256 hardware architecture with compact message expander for bitcoin mining
HL Pham, TH Tran, TD Phan, VTD Le, DK Lam, Y Nakashima
IEEE Access 8, 139634-139646, 2020
Practical anti-counterfeit medicine management system based on blockchain technology
HL Pham, TH Tran, Y Nakashima
2019 4TH technology innovation management and engineering science …, 2019
An instruction mapping scheme for FU array accelerator
K Yoshimura, T Iwakami, T Nakada, J Yao, H Shimada, Y Nakashima
IEICE TRANSACTIONS on Information and Systems 94 (2), 286-297, 2011
Cellular neural network formed by simplified processing elements composed of thin-film transistors
M Kimura, R Morita, S Sugisaki, T Matsuda, T Kameda, Y Nakashima
Neurocomputing 248, 112-119, 2017
Amorphous metal oxide semiconductor thin film, analog memristor, and autonomous local learning for neuromorphic systems
M Kimura, R Sumida, A Kurasaki, T Imai, Y Takishita, Y Nakashima
Scientific reports 11 (1), 580, 2021
Digitizing invoice and managing vat payment using blockchain smart contract
VC Nguyen, P Hoai-Luan, T Thi-Hong, HT Huynh, Y Nakashima
2019 IEEE International Conference on Blockchain and Cryptocurrency (ICBC …, 2019
A high-performance multimem SHA-256 accelerator for society 5.0
TH Tran, HL Pham, Y Nakashima
IEEE Access 9, 39182-39192, 2021
DARA: A low-cost reliable architecture based on unhardened devices and its case study of radiation stress test
J Yao, S Okada, M Masuda, K Kobayashi, Y Nakashima
IEEE Transactions on Nuclear Science 59 (6), 2852-2858, 2012
Outline of OROCHI: A Multiple Instruction Set Executable SMT Processor
H Shimada, T Shimada, T Tabata, T Kitamura, T Kojima, Y Nakashima, ...
Innovative architecture for future generation high-performance processors …, 2007
Memristive characteristic of an amorphous Ga-Sn-O thin-film device
S Sugisaki, T Matsuda, M Uenuma, T Nabatame, Y Nakashima, T Imai, ...
Scientific Reports 9 (1), 2757, 2019
IEICE Technical Report
N Honda, H Yasuda, M Hasegawa
MR2005-15 (2005-06)(in Japanese), 2009
A high-efficiency FPGA-based multimode SHA-2 accelerator
HL Pham, TH Tran, VTD Le, Y Nakashima
IEEE Access 10, 11830-11845, 2022
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