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Robert R Robison
Robert R Robison
IBM Research
Verified email at us.ibm.com
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Cited by
Year
Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET
N Loubet, T Hook, P Montanini, CW Yeung, S Kanakasabapathy, ...
2017 symposium on VLSI technology, T230-T231, 2017
7712017
High performance 14nm SOI FinFET CMOS technology with 0.0174µm2 embedded DRAM and 15 levels of Cu metallization
CH Lin, B Greene, S Narasimha, J Cai, A Bryant, C Radens, V Narayanan, ...
2014 IEEE International Electron Devices Meeting, 3.8. 1-3.8. 3, 2014
1802014
High performance low power bulk FET device and method of manufacture
J Cai, T Furukawa, RR Robison
US Patent 8,361,872, 2013
1292013
22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL
S Narasimha, P Chang, C Ortolland, D Fried, E Engbrecht, K Nummy, ...
2012 International Electron Devices Meeting, 3.3. 1-3.3. 4, 2012
1032012
Channel geometry impact and narrow sheet effect of stacked nanosheet
CW Yeung, J Zhang, R Chao, O Kwon, R Vega, G Tsutsui, X Miao, ...
2018 IEEE international electron devices meeting (IEDM), 28.6. 1-28.6. 4, 2018
762018
FINFET technology featuring high mobility SiGe channel for 10nm and beyond
D Guo, G Karve, G Tsutsui, KY Lim, R Robison, T Hook, R Vega, D Liu, ...
2016 IEEE Symposium on VLSI Technology, 1-2, 2016
652016
Full bottom dielectric isolation to enable stacked nanosheet transistor for low power and high performance applications
J Zhang, J Frougier, A Greene, X Miao, L Yu, R Vega, P Montanini, ...
2019 IEEE International Electron Devices Meeting (IEDM), 11.6. 1-11.6. 4, 2019
642019
Observation of fluorine-vacancy complexes in silicon
PJ Simpson, Z Jenei, P Asoka-Kumar, RR Robison, ME Law
Applied physics letters 85 (9), 1538-1540, 2004
412004
Vertical-transport nanosheet technology for CMOS scaling beyond lateral-transport devices
H Jagannathan, B Anderson, CW Sohn, G Tsutsui, J Strane, R Xie, S Fan, ...
2021 IEEE International Electron Devices Meeting (IEDM), 26.1. 1-26.1. 4, 2021
312021
Butted SOI junction isolation structures and devices and method of fabrication
JB Johnson, S Narasimha, HM Nayfeh, V Ontalus, RR Robison
US Patent 8,741,725, 2014
252014
Enhanced stress-retention silicon-on-insulator devices and methods of fabricating enhanced stress retention silicon-on-insulator devices
KV Chatty, RJ Gauthier Jr, JH Rankin, RR Robison, WR Tonti
US Patent 7,737,498, 2010
252010
Vertical field effect transistor with subway etch replacement metal gate
RR Robison, RA Vega, R Venigalla
US Patent 9,859,421, 2018
232018
Vertical fin field effect transistor with air gap spacers
HV Mallela, RR Robison, RA Vega, R Venigalla
US Patent 9,911,804, 2018
222018
Nanosheet MOSFET with partial release and source/drain epitaxy
MA Guillorn, TB Hook, NJ Loubet, RR Robison, RA Vega
US Patent 10,249,739, 2019
202019
Semiconductor-on-insulator (SOI) structure with selectively placed sub-insulator layer void (s) and method of forming the SOI structure
T Furukawa, RR Robison, RQ Williams
US Patent 8,610,211, 2013
202013
First-Principles Evaluation of fcc Ruthenium for its use in Advanced Interconnects
TM Philip, NA Lanzillo, T Gunst, T Markussen, J Cobb, S Aboud, ...
Physical Review Applied 13 (4), 044045, 2020
192020
Vertical field effect transistors with metallic source/drain regions
HV Mallela, RR Robison, R Vega, R Venigalla
US Patent 9,728,466, 2017
172017
Submicron mapping of strain distributions induced by three-dimensional through-silicon via features
CE Murray, T Graves-Abe, R Robison, Z Cai
Applied Physics Letters 102 (25), 2013
162013
Impact of lateral asymmetric channel doping on 45-nm-technology N-type SOI MOSFETs
HM Nayfeh, N Rovedo, A Bryant, S Narasimha, A Kumar, X Yu, N Su, ...
IEEE transactions on electron devices 56 (12), 3097-3105, 2009
162009
Vertical field effect transistors with metallic source/drain regions
HV Mallela, RR Robison, R Vega, R Venigalla
US Patent 9,859,384, 2018
152018
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