| The gem5 simulator N Binkert, B Beckmann, G Black, SK Reinhardt, A Saidi, A Basu, ... ACM SIGARCH computer architecture news 39 (2), 1-7, 2011 | 6118 | 2011 |
| Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset MMK Martin, DJ Sorin, BM Beckmann, MR Marty, M Xu, AR Alameldeen, ... ACM SIGARCH Computer Architecture News 33 (4), 92-99, 2005 | 2117 | 2005 |
| Implementation techniques for main memory database systems DJ DeWitt, RH Katz, F Olken, LD Shapiro, MR Stonebraker, DA Wood ACM SIGMOD Record 14 (2), 1-8, 1984 | 1349 | 1984 |
| LogTM: Log-based transactional memory KE Moore, J Bobba, MJ Moravan, MD Hill, DA Wood Proceedings of the 12th International Symposium on High-Performance Computer …, 2006 | 974 | 2006 |
| DBMSs on a modern processor: Where does time go? A Ailamaki, DJ DeWitt, MD Hill, DA Wood Proceedings of the International Conference on Very Large Data Bases, 266-277, 1999 | 766 | 1999 |
| Tempest and Typhoon: User-level shared memory SK Reinhardt, JR Larus, DA Wood Proceedings of the 21st annual international symposium on Computer …, 1994 | 554 | 1994 |
| A primer on memory consistency and cache coherence D Sorin, M Hill, D Wood Springer Nature, 2022 | 524 | 2022 |
| The wisconsin wind tunnel: Virtual prototyping of parallel computers SK Reinhardt, MD Hill, JR Larus, AR Lebeck, JC Lewis, DA Wood Proceedings of the 1993 ACM SIGMETRICS conference on Measurement and …, 1993 | 524 | 1993 |
| Managing wire delay in large chip-multiprocessor caches BM Beckmann, DA Wood 37th International Symposium on Microarchitecture (MICRO-37'04), 319-330, 2004 | 500 | 2004 |
| LogTM-SE: Decoupling hardware transactional memory from caches L Yen, J Bobba, MR Marty, KE Moore, H Volos, MD Hill, MM Swift, ... 2007 IEEE 13th International Symposium on High Performance Computer …, 2007 | 472 | 2007 |
| Adaptive cache compression for high-performance processors AR Alameldeen, DA Wood ACM SIGARCH Computer Architecture News 32 (2), 212, 2004 | 439 | 2004 |
| SafetyNet: Improving the availability of shared memory multiprocessors with global checkpoint/recovery DJ Sorin, MMK Martin, MD Hill, DA Wood ACM SIGARCH Computer Architecture News 30 (2), 123-134, 2002 | 428 | 2002 |
| Token coherence: Decoupling performance and correctness MMK Martin, MD Hill, DA Wood ACM SIGARCH Computer Architecture News 31 (2), 182-193, 2003 | 422 | 2003 |
| Implementing a cache consistency protocol RH Katz, SJ Eggers, DA Wood, CL Perkins, RG Sheldon ACM SIGARCH Computer Architecture News 13 (3), 276-283, 1985 | 418 | 1985 |
| Fine-grain access control for distributed shared memory I Schoinas, B Falsafi, AR Lebeck, SK Reinhardt, JR Larus, DA Wood Proceedings of the sixth international conference on Architectural support …, 1994 | 392 | 1994 |
| Frequent pattern compression: A significance-based compression scheme for L2 caches AR Alameldeen, DA Wood Dept. of Computer Sciences, University of Wisconsin-Madison, Tech. Rep, 2004 | 364 | 2004 |
| Variability in architectural simulations of multi-threaded workloads AR Alameldeen, DA Wood The Ninth International Symposium on High-Performance Computer Architecture …, 2003 | 359 | 2003 |
| Cache profiling and the SPEC benchmarks: A case study AR Lebeck, DA Wood Computer 27 (10), 15-26, 1994 | 344 | 1994 |
| gem5-gpu: A heterogeneous cpu-gpu simulator J Power, J Hestness, MS Orr, MD Hill, DA Wood IEEE Computer Architecture Letters 14 (1), 34-36, 2014 | 328 | 2014 |
| Performance pathologies in hardware transactional memory J Bobba, KE Moore, H Volos, L Yen, MD Hill, MM Swift, DA Wood ACM SIGARCH Computer Architecture News 35 (2), 81-91, 2007 | 324 | 2007 |
Mark D. HillUniversity of Wisconsin-Madison Professor EmeritusVerified email at cs.wisc.edu
