| Accuracy vs. efficiency: Achieving both through fpga-implementation aware neural architecture search W Jiang, X Zhang, EHM Sha, L Yang, Q Zhuge, Y Shi, J Hu Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 100 | 2019 |
| Hardware/software co-exploration of neural architectures W Jiang, L Yang, EHM Sha, Q Zhuge, S Gu, S Dasgupta, Y Shi, J Hu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020 | 83 | 2020 |
| Co-exploration of neural architectures and heterogeneous asic accelerator designs targeting multiple tasks L Yang, Z Yan, M Li, H Kwon, L Lai, T Krishna, V Chandra, W Jiang, Y Shi 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 59 | 2020 |
| Achieving super-linear speedup across multi-fpga for real-time dnn inference W Jiang, EHM Sha, X Zhang, L Yang, Q Zhuge, Y Shi, J Hu ACM Transactions on Embedded Computing Systems (TECS) 18 (5s), 1-23, 2019 | 53 | 2019 |
| GESS: a database of global evaluation of SARS-CoV-2/hCoV-19 sequences S Fang, K Li, J Shen, S Liu, J Liu, L Yang, CD Hu, J Wan Nucleic acids research 49 (D1), D706-D714, 2021 | 50 | 2021 |
| Device-circuit-architecture co-exploration for computing-in-memory neural accelerators W Jiang, Q Lou, Z Yan, L Yang, J Hu, XS Hu, Y Shi IEEE Transactions on Computers 70 (4), 595-605, 2020 | 41 | 2020 |
| Genetic spectrum and distinct evolution patterns of SARS-CoV-2 S Liu, J Shen, S Fang, K Li, J Liu, L Yang, CD Hu, J Wan Frontiers in microbiology, 2390, 2020 | 39 | 2020 |
| Task mapping on SMART NoC: Contention matters, not the distance L Yang, W Liu, P Chen, N Guan, M Li Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017 | 38 | 2017 |
| Standing on the shoulders of giants: Hardware and neural architecture co-search with hot start W Jiang, L Yang, S Dasgupta, J Hu, Y Shi IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020 | 37 | 2020 |
| Application mapping and scheduling for network-on-chip-based multiprocessor system-on-chip with fine-grain communication optimization L Yang, W Liu, W Jiang, M Li, J Yi, EHM Sha IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (10 …, 2016 | 35 | 2016 |
| FoToNoC: A folded torus-like network-on-chip based many-core systems-on-chip in the dark silicon era L Yang, W Liu, W Jiang, M Li, P Chen, EHM Sha IEEE Transactions on Parallel and Distributed Systems 28 (7), 1905-1918, 2016 | 33 | 2016 |
| Heterogeneous fpga-based cost-optimal design for timing-constrained cnns W Jiang, EHM Sha, Q Zhuge, L Yang, X Chen, J Hu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 26 | 2018 |
| Co-exploring neural architecture and network-on-chip design for real-time artificial intelligence L Yang, W Jiang, W Liu, HM Edwin, Y Shi, J Hu 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), 85-90, 2020 | 25 | 2020 |
| Thermal-aware task mapping on dynamically reconfigurable network-on-chip based multiprocessor system-on-chip W Liu, L Yang, W Jiang, L Feng, N Guan, W Zhang, N Dutt IEEE Transactions on Computers 67 (12), 1818-1834, 2018 | 25 | 2018 |
| Chip temperature optimization for dark silicon many-core systems M Li, W Liu, L Yang, P Chen, C Chen IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 21 | 2017 |
| FoToNoC: A hierarchical management strategy based on folded torus-like network-on-chip for dark silicon many-core systems L Yang, W Liu, W Jiang, M Li, J Yi, EHM Sha 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 725-730, 2016 | 16 | 2016 |
| Dark silicon-aware hardware-software collaborated design for heterogeneous many-core systems L Yang, W Liu, N Guan, M Li, P Chen, HM Edwin 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 494-499, 2017 | 13 | 2017 |
| Energy-efficient application mapping and scheduling for lifetime guaranteed MPSoCs W Liu, J Yi, M Li, P Chen, L Yang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 12 | 2018 |
| Xfer: A novel design to achieve super-linear performance on multiple fpgas for real-time ai W Jiang, X Zhang, EHM Sha, Q Zhuge, L Yang, Y Shi, J Hu Proceedings of the 2019 ACM/SIGDA International Symposium on Field …, 2019 | 10 | 2019 |
| Optimal application mapping and scheduling for network-on-chips with computation in STT-RAM based router L Yang, W Liu, N Guan, N Dutt IEEE Transactions on Computers 68 (8), 1174-1189, 2018 | 10 | 2018 |
Weiwen JiangGeorge Mason UniversityVerified email at gmu.edu
