Paul Molitor
Paul Molitor
Martin Luther University Halle-Wittenberg, Institute for Computer Science
Bestätigte E-Mail-Adresse bei - Startseite
Zitiert von
Zitiert von
Using Sifting for k-Layer Straightline Crossing Minimization
C Matuszewski, R Schönfeld, P Molitor
International Symposium on Graph Drawing, 217-224, 1999
BDD minimization using symmetries
C Scholl, D Moller, P Molitor, R Drechsler
IEEE transactions on computer-aided design of integrated circuits and …, 1999
Limits of using signatures for permutation independent Boolean comparison
J Mohnke, P Molitor, S Malik
Formal Methods in System Design 21 (2), 167-191, 2002
A pipelined architecture for partitioned DWT based lossy image compression using FPGA's
J Ritter, P Molitor
Proceedings of the 2001 ACM/SIGDA ninth international symposium on field …, 2001
Polynomial formal verification of multipliers
M Keim, R Drechsler, B Becker, M Martin, P Molitor
Formal Methods in System Design 22 (1), 39-58, 2003
Equivalence checking of digital circuits: fundamentals, principles, methods
P Molitor, J Mohnke
Springer Science & Business Media, 2007
Hierarchical design based on a calculus of nets
B Becker, G Hotz, R Kolla, P Molitor, HG Osthof
Proceedings of the 24th ACM/IEEE Design Automation Conference, 649-653, 1987
Technische Informatik
B Becker, P Molitor
Technische Informatik, 2009
Symmetry based variable ordering for ROBDDs
D Möller, P Molitor, R Drechsler
Logic and Architecture Synthesis, 70-81, 1995
Exact algorithms and heuristics for the quadratic traveling salesman problem with an application in bioinformatics
A Fischer, F Fischer, G Jäger, J Keilwagen, P Molitor, I Grosse
Discrete Applied Mathematics 166, 97-114, 2014
Algorithms and experimental study for the traveling salesman problem of second order
G Jäger, P Molitor
International Conference on Combinatorial Optimization and Applications …, 2008
Tolerances applied in combinatorial optimization
B Goldengorin, G Jäger, P Molitor
J. Comput. Sci 2 (9), 716-734, 2006
Minimizing ROBDD sizes of incompletely specified Boolean functions by exploiting strong symmetries
C Scholl, S Melchior, G Hotz, P Molitor
Proceedings European Design and Test Conference. ED & TC 97, 229-234, 1997
A survey on wiring
P Molitor
Elektronische Informationsverarbeitung und Kybernetik 27 (1), 3-19, 1991
Communication based FPGA synthesis for multi-output Boolean functions
C Scholl, P Molitor
Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair, 279-287, 1995
Least upper bounds for the size of OBDDs using symmetry properties
L Heinrich-Litan, P Molitor
IEEE Transactions on computers 49 (4), 360-368, 2000
Einführung in den VLSI-Entwurf
R Kolla, P Molitor, HG Osthof
A Graphical System for Hierarchical Specifications and Checkups of VLSI Circuits’
G Hotz, B Becker, T Burch, P Molitor, D Kiel, R Kolla, U Sparmann, ...
The Proceedings of the European Design Automation Conference, 174, 1990
Kompaktkurs VHDL
P Molitor, J Ritter
Kompaktkurs VHDL, 2013
On the generation of area-time optimal testable adders
B Becker, R Drechsler, P Molitor
IEEE transactions on computer-aided design of integrated circuits and …, 1995
Das System kann den Vorgang jetzt nicht ausführen. Versuchen Sie es später erneut.
Artikel 1–20