| Managing mismatches in voltage stacking with coreunfolding EK Ardestani, RT Possignolo, JL Briz, J Renau ACM Transactions on Architecture and Code Optimization (TACO) 12 (4), 1-26, 2015 | 20 | 2015 |
| LGraph: A unified data model and API for productive open-source hardware design SH Wang, RT Possignolo, Q Chen, R Ganpati, J Renau Proc. 2nd Workshop Open-Source EDA Technol., 2019 | 17 | 2019 |
| LiveSynth: Towards an interactive synthesis flow RT Possignolo, J Renau Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017 | 17 | 2017 |
| Gpu ntc process variation compensation with voltage stacking RT Possignolo, E Ebrahimi, EK Ardestani, A Sankaranarayanan, JL Briz, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (9 …, 2018 | 16 | 2018 |
| Automated extra pipeline analysis of applications mapped to Xilinx UltraScale+ FPGAs I Ganusov, H Fraisse, A Ng, RT Possignolo, S Das 2016 26th International Conference on Field Programmable Logic and …, 2016 | 16 | 2016 |
| Fluid pipelines: Elastic circuitry meets out-of-order execution RT Possignolo, E Ebrahimi, H Skinner, J Renau 2016 IEEE 34th International Conference on Computer Design (ICCD), 233-240, 2016 | 15 | 2016 |
| Livehd: A productive live hardware development flow SH Wang, RT Possignolo, HB Skinner, J Renau IEEE Micro 40 (4), 67-75, 2020 | 14 | 2020 |
| Level shifter design for voltage stacking E Ebrahimi, RT Possignolo, J Renau 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017 | 14 | 2017 |
| FluidPipelines: Elastic circuitry without throughput penalty RT Possignolo, E Ebrahimi, H Skinner, J Renau Logic Synthesis (IWLS), Proceedings of the 2016 International Workshop on, 2016 | 11 | 2016 |
| LGraph: A multi-language open-source database for VLSI RT Possignolo, SH Wang, H Skinner, J Renau | 11* | |
| ANUBIS: A new benchmark for incremental synthesis RT Possignolo, N Kabylkas, J Renau Proc. Int. Workshop Logic Synthesis, 8, 2017 | 10 | 2017 |
| SRAM voltage stacking E Ebrahimi, RT Possignolo, J Renau 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 1634-1637, 2016 | 10 | 2016 |
| LiveSim: A fast hot reload simulator for HDLs H Skinner, RT Possignolo, SH Wang, J Renau 2020 IEEE International Symposium on Performance Analysis of Systems and …, 2020 | 9* | 2020 |
| SMatch: Structural matching for fast resynthesis in FPGAS RT Possignolo, J Renau Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 8 | 2019 |
| A Quantum-classical Hybrid Architecture for Security Algorithms Acceleration RT Possignolo, CB Margi Trust, Security and Privacy in Computing and Communications (TrustCom), 2012 …, 2012 | 8 | 2012 |
| Liam: an actor based programming model for hdls H Skinner, RT Possignolo, J Renau Proceedings of the 15th ACM-IEEE International Conference on Formal Methods …, 2017 | 6 | 2017 |
| Projeto de um coprocessador quântico para otimização de algoritmos criptográficos. RT Possignolo Universidade de São Paulo, 2012 | 6 | 2012 |
| Performance evaluation of QoS in wireless networks using IEEE 802.11 e LBV Boas, PM Massolino, RT Possignolo, CB Margi, RM Silveira Proceedings of the SIMPÓSIO BRASILEIRO DE TELECOMUNICAÇÕES, 1-5, 2012 | 5 | 2012 |
| Structural matching for fast re-synthesis of electronic circuits R Possignolo, J Renau US Patent 10,885,246, 2021 | 4 | 2021 |
| Pyrope H Skinner, SH Wang, A Sridhar, RT Possignolo, K Mayer, J Renau | 4 | 2019 |
Jose RenauProcessor of Computer Science Engineering, UCSCBestätigte E-Mail-Adresse bei ucsc.edu
