Folgen
Rafael Trapani Possignolo
Rafael Trapani Possignolo
Bestätigte E-Mail-Adresse bei intel.com - Startseite
Titel
Zitiert von
Zitiert von
Jahr
Managing mismatches in voltage stacking with coreunfolding
EK Ardestani, RT Possignolo, JL Briz, J Renau
ACM Transactions on Architecture and Code Optimization (TACO) 12 (4), 1-26, 2015
202015
LiveSynth: Towards an interactive synthesis flow
RT Possignolo, J Renau
Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017
162017
Automated extra pipeline analysis of applications mapped to Xilinx UltraScale+ FPGAs
I Ganusov, H Fraisse, A Ng, RT Possignolo, S Das
2016 26th International Conference on Field Programmable Logic and …, 2016
162016
Fluid pipelines: Elastic circuitry meets out-of-order execution
RT Possignolo, E Ebrahimi, H Skinner, J Renau
2016 IEEE 34th International Conference on Computer Design (ICCD), 233-240, 2016
142016
LGraph: A unified data model and API for productive open-source hardware design
SH Wang, RT Possignolo, Q Chen, R Ganpati, J Renau
Proc. 2nd Workshop Open-Source EDA Technol., 2019
132019
Gpu ntc process variation compensation with voltage stacking
RT Possignolo, E Ebrahimi, EK Ardestani, A Sankaranarayanan, JL Briz, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (9 …, 2018
132018
FluidPipelines: Elastic circuitry without throughput penalty
RT Possignolo, E Ebrahimi, H Skinner, J Renau
Logic Synthesis (IWLS), Proceedings of the 2016 International Workshop on, 2016
132016
LGraph: A multi-language open-source database for VLSI
RT Possignolo, SH Wang, H Skinner, J Renau
12*
Level shifter design for voltage stacking
E Ebrahimi, RT Possignolo, J Renau
2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017
112017
SRAM voltage stacking
E Ebrahimi, RT Possignolo, J Renau
2016 IEEE International Symposium on Circuits and Systems (ISCAS), 1634-1637, 2016
102016
ANUBIS: A new benchmark for incremental synthesis
RT Possignolo, N Kabylkas, J Renau
Proc. Int. Workshop Logic Synthesis, 8, 2017
92017
Livehd: A productive live hardware development flow
SH Wang, RT Possignolo, HB Skinner, J Renau
IEEE Micro 40 (4), 67-75, 2020
72020
SMatch: Structural matching for fast resynthesis in FPGAS
RT Possignolo, J Renau
Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019
72019
Liam: an actor based programming model for hdls
H Skinner, RT Possignolo, J Renau
Proceedings of the 15th ACM-IEEE International Conference on Formal Methods …, 2017
62017
A Quantum-classical Hybrid Architecture for Security Algorithms Acceleration
RT Possignolo, CB Margi
Trust, Security and Privacy in Computing and Communications (TrustCom), 2012 …, 2012
52012
Pyrope
H Skinner, SH Wang, A Sridhar, RT Possignolo, K Mayer, J Renau
42019
Performance evaluation of QoS in wireless networks using IEEE 802.11 e
LBV Boas, PM Massolino, RT Possignolo, CB Margi, RM Silveira
Proceedings of the SIMPÓSIO BRASILEIRO DE TELECOMUNICAÇÕES, 1-5, 2012
42012
Optimized joint NARX ANN-embedded processor design methodology
RT Possignolo, O Hammami
2009 16th IEEE International Conference on Electronics, Circuits and Systems …, 2009
42009
LiveSynth: towards an interactive synthesis flow. Poster at the 28th HotChips: A Symposium on High Performance Chips
R Possignolo, J Renau
https://users.soe.ucsc.edu/~renau/docs/hotchips16.pdf, 0
4
LiveSim: A Fast Hot Reload Simulator for HDLs
H Skinner, RT Possignolo, SH Wang, J Renau
2020 IEEE International Symposium on Performance Analysis of Systems and …, 2020
32020
Das System kann den Vorgang jetzt nicht ausführen. Versuchen Sie es später erneut.
Artikel 1–20