| An Uninterrupted Processing Technique-Based High-Throughput and Energy-Efficient Hardware Accelerator for Convolutional Neural Networks MN Islam, R Shrestha, SR Chowdhury IEEE Transactions on Very Large Scale Integration (VLSI) Systems 30 (12 …, 2022 | 3 | 2022 |
| A New Hardware-Efficient VLSI-Architecture of GoogLeNet CNN-Model Based Hardware Accelerator for Edge Computing Applications MN Islam, R Shrestha, SR Chowdhury 2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 414-417, 2022 | 3 | 2022 |
| A 10-bit 2.33 fJ/conv. SAR-ADC with high speed capacitive DAC switching using a novel effective asynchronous control circuitry F Begum, S Mishra, MN Islam, A Dandapat Analog Integrated Circuits and Signal Processing 100, 311-325, 2019 | 1 | 2019 |
| Low-Complexity lassification Technique and Hardware-Efficient Classify-Unit Architecture for CNN Accelerator MN Islam, R Shrestha, SR Chowdhury 2024 37th International Conference on VLSI Design and 2024 23rd …, 2024 | | 2024 |
| Analysis and Proposal of a Flash Subranging ADC Architecture F Begum, S Mishra, M Najrul Islam, A Dandapat Proceedings of the Third International Conference on Microelectronics …, 2019 | | 2019 |
Rahul ShresthaAssociate Professor, IIT Mandi確認したメール アドレス: iitmandi.ac.in
