Jeronimo Castrillon
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MAPS: an integrated framework for MPSoC application parallelization
J Ceng, J Castrillón, W Sheng, H Scharwächter, R Leupers, G Ascheid, ...
Proceedings of the 45th annual Design Automation Conference, 754-759, 2008
MAPS: Mapping Concurrent Dataflow Applications to Heterogeneous MPSoCs
J Castrillon, R Leupers, G Ascheid
IEEE Transactions on Industrial Informatics 1 (9), 527--545, 2013
The gem5 simulator: Version 20.0+
J Lowe-Power, AM Ahmad, A Akram, M Alian, R Amslinger, M Andreozzi, ...
arXiv preprint arXiv:2007.03152, 2020
Programming Heterogeneous MPSoCs
J Castrillón Mazo, R Leupers
Springer International Pu, 2013
Programming heterogeneous MPSoCs: tool flows to close the software productivity gap
J Castrillon
Lehrstuhl für Software für Systeme auf Silizium, RWTH Aachen, 2013
Communication-aware mapping of KPN applications onto heterogeneous MPSoCs
J Castrillon, A Tretter, R Leupers, G Ascheid
Proceedings of the 49th Annual Design Automation Conference, 1266-1271, 2012
Magnetic racetrack memory: From physics to the cusp of applications within a decade
R Bläsing, AA Khan, PC Filippou, C Garg, F Hameed, J Castrillon, ...
Proceedings of the IEEE 108 (8), 1303-1321, 2020
A high-level virtual platform for early MPSoC software development
J Ceng, W Sheng, J Castrillon, A Stulova, R Leupers, G Ascheid, H Meyr
Proceedings of the 7th IEEE/ACM international conference on Hardware …, 2009
MPSoC programming using the MAPS compiler
R Leupers, J Castrillon
2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 897-902, 2010
Compiler-based graph representations for deep learning models of code
A Brauckmann, A Goens, S Ertel, J Castrillon
Proceedings of the 29th International Conference on Compiler Construction …, 2020
Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms
J Castrillon, R Velasquez, A Stulova, W Sheng, J Ceng, R Leupers, ...
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010
Task management in MPSoCs: An ASIP approach
J Castrillon, D Zhang, T Kempf, B Vanthournout, R Leupers, G Ascheid
Proceedings of the 2009 International Conference on Computer-Aided Design …, 2009
System Simulation with gem5 and SystemC: The Keystone for Full Interoperability
C Menard, J Castrillon, M Jung, N Wehn
Proceedings of the IEEE International Conference on Embedded Computer …, 2017
Reactors: A deterministic model for composable reactive systems
M Lohstroh, ÍÍ Romeo, A Goens, P Derler, J Castrillon, EA Lee, ...
Cyber Physical Systems. Model-Based Design: 9th International Workshop …, 2020
Shiftsreduce: Minimizing shifts in racetrack memory 4.0
AA Khan, F Hameed, R Bläsing, SSP Parkin, J Castrillon
ACM Transactions on Architecture and Code Optimization (TACO) 16 (4), 1-23, 2019
Architecture and advanced electronics pathways toward highly adaptive energy-efficient computing
GP Fettweis, M Dörpinghaus, J Castrillon, A Kumar, C Baier, K Bock, ...
Proceedings of the IEEE 107 (1), 204-231, 2018
Tetris: a multi-application run-time system for predictable execution of static mappings
A Goens, R Khasanov, J Castrillon, M Hähnel, T Smejkal, H Härtig
Proceedings of the 20th International Workshop on Software and Compilers for …, 2017
Performance and energy-efficient design of STT-RAM last-level cache
F Hameed, AA Khan, J Castrillon
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (6 …, 2018
CFDlang: High-level code generation for high-order methods in fluid dynamics
NA Rink, I Huismann, A Susungi, J Castrillon, J Stiller, J Fröhlich, ...
Proceedings of the Real World Domain Specific Languages Workshop 2018, 1-10, 2018
RTSim: A cycle-accurate simulator for racetrack memories
AA Khan, F Hameed, R Bläsing, S Parkin, J Castrillon
IEEE Computer Architecture Letters 18 (1), 43-46, 2019
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