Viktor Puš
Viktor Puš
Researcher at CESNET
Verified email at cesnet.cz - Homepage
Title
Cited by
Cited by
Year
Software defined monitoring of application protocols
L Kekely, J Kučera, V Puš, J Kořenek, AV Vasilakos
IEEE Transactions on Computers 65 (2), 615-626, 2015
612015
Fast and scalable packet classification using perfect hash functions
V Puš, J Korenek
Proceedings of the ACM/SIGDA international symposium on Field programmable …, 2009
462009
Netbench: Framework for evaluation of packet processing algorithms
V Pus, J Tobola, V Kosar, J Kastil, J Korenek
2011 ACM/IEEE Seventh Symposium on Architectures for Networking and …, 2011
252011
Low-latency modular packet header parser for FPGA
V Puš, L Kekely, J Kořenek
2012 ACM/IEEE Symposium on Architectures for Networking and Communications …, 2012
242012
P4-To-VHDL: Automatic generation of high-speed input and output network blocks
P Benáček, V Puš, H Kubátová, T Čejka
Microprocessors and Microsystems 56, 22-33, 2018
152018
Design methodology of configurable high performance packet parser for FPGA
V Puš, L Kekely, J Kořenek
17th International Symposium on Design and Diagnostics of Electronic …, 2014
132014
High-speed regular expression matching with pipelined automata
D Matoušek, J Kořenek, V Puš
2016 International Conference on Field-Programmable Technology (FPT), 93-100, 2016
102016
Hardware accelerated flow measurement of 100 Gb ethernet
V Puš, P Velan, L Kekely, J Kořenek, P Minařík
2015 IFIP/IEEE International Symposium on Integrated Network Management (IM …, 2015
102015
Trade-offs and progressive adoption of FPGA acceleration in network traffic monitoring
L Kekely, V Puš, P Benáček, J Kořenek
2014 24th International Conference on Field Programmable Logic and …, 2014
102014
Configurable FPGA packet parser for terabit networks with guaranteed wire-speed throughput
J Cabal, P Benáček, L Kekely, M Kekely, V Puš, J Kořenek
Proceedings of the 2018 ACM/SIGDA International Symposium on Field …, 2018
92018
Line rate programmable packet processing in 100Gb networks
P Benáček, V Puš, J Kořenek, M Kekely
2017 27th International Conference on Field Programmable Logic and …, 2017
62017
High-density network flow monitoring
P Velan, V Puš
2015 IFIP/IEEE International Symposium on Integrated Network Management (IM …, 2015
52015
CRC based hashing in FPGA using DSP blocks
T Závodník, L Kekely, V Puš
17th International Symposium on Design and Diagnostics of Electronic …, 2014
52014
Hardware acceleration for measurements in 100 gb/s networks
V Puš
IFIP International Conference on Autonomous Infrastructure, Management and …, 2012
52012
Memory optimization for packet classification algorithms
J Blaho, J Kořenek, V Puš
Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking …, 2009
52009
Hardware architecture for packet classification with prefix coloring
V Puš, M Kajan, J KoŸenek
14th IEEE International Symposium on Design and Diagnostics of Electronic …, 2011
32011
Packet Classification Algorithms.
V Puš
Information Sciences & Technologies: Bulletin of the ACM Slovakia 4 (4), 2012
22012
SystemVerilog verification of VHDL design
P Kobierský, T Málek, V Puš, D Šafránek
Technical Report 35, CESNET zspo, 2007
22007
Demonstration of Full-Duplex Packet Transfers Over PCI Express with Sustained 200 Gbps Throughput
L Kekely, M Špinler, Š Friedl, J Sikora, J Kořenek, V Puš
2018 International Conference on Field-Programmable Technology (FPT), 381-384, 2018
12018
Verification of generated rtl from p4 source code
R Iša, P Benáček, V Puš
2018 IEEE 26th International Conference on Network Protocols (ICNP), 444-445, 2018
12018
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Articles 1–20