| Repeated on-chip interconnect analysis and evaluation of delay, power, and bandwidth metrics under different design goals L Zhang, H Chen, B Yao, K Hamilton, CK Cheng 8th International Symposium on Quality Electronic Design (ISQED'07), 251-256, 2007 | 32 | 2007 |
| Prediction and comparison of high-performance on-chip global interconnection Y Zhang, X Hu, A Deutsch, AE Engin, JF Buckwalter, CK Cheng IEEE transactions on very large scale integration (VLSI) systems 19 (7 …, 2010 | 22 | 2010 |
| Process variation compensation of a 2.4 GHz LNA in 0.18 um CMOS using digitally switchable capacitance Y Cui, B Chi, M Liu, Y Zhang, Y Li, Z Wang, P Chiang 2007 IEEE International Symposium on Circuits and Systems, 2562-2565, 2007 | 20 | 2007 |
| Energy efficiency optimization through codesign of the transmitter and receiver in high-speed on-chip interconnects SH Weng, Y Zhang, JF Buckwalter, CK Cheng IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (4), 938-942, 2013 | 18 | 2013 |
| Design methodology of high performance on-chip global interconnect using terminated transmission-line Y Zhang, L Zhang, A Deutsch, GA Katopis, DM Dreps, JF Buckwalter, ... 2009 10th International Symposium on Quality Electronic Design, 451-458, 2009 | 18 | 2009 |
| High performance on-chip differential signaling using passive compensation for global communication L Zhang, Y Zhang, A Tsuchiya, M Hashimoto, ES Kuh, CK Cheng 2009 Asia and South Pacific Design Automation Conference, 385-390, 2009 | 17 | 2009 |
| Fast power network analysis with multiple clock domains W Zhang, L Zhang, R Shi, H Peng, Z Zhu, L Chua-Eoan, R Murgai, ... 2007 25th International Conference on Computer Design, 456-463, 2007 | 16 | 2007 |
| Low power passive equalizer design for computer memory links L Zhang, W Yu, Y Zhang, R Wang, A Deutsch, GA Katopis, DM Dreps, ... 2008 16th IEEE Symposium on High Performance Interconnects, 51-56, 2008 | 13 | 2008 |
| Efficient power network analysis considering multidomain clock gating W Zhang, W Yu, X Hu, L Zhang, R Shi, H Peng, Z Zhu, L Chua-Eoan, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2009 | 11 | 2009 |
| On the bound of time-domain power supply noise based on frequency-domain target impedance X Hu, W Zhao, P Du, Y Zhang, A Shayan, C Pan, AE Egin, CK Cheng Proceedings of the 11th international workshop on System level interconnect …, 2009 | 11 | 2009 |
| Low power passive equalizer optimization using tritonic step response L Zhang, W Yu, H Zhu, A Deutsch, GA Katopis, DM Dreps, E Kuh, ... Proceedings of the 45th annual Design Automation Conference, 570-573, 2008 | 11 | 2008 |
| On-chip global clock distribution using directional rotary traveling-wave oscillator Y Zhang, JF Buckwalter, CK Cheng 2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging …, 2009 | 10 | 2009 |
| High-speed and low-power on-chip global link using continuous-time linear equalizer Y Zhang, JF Buckwalter, CK Cheng 19th Topical Meeting on Electrical Performance of Electronic Packaging and …, 2010 | 9 | 2010 |
| On-chip interconnect analysis of performance and energy metrics under different design goals L Zhang, Y Zhang, H Chen, B Yao, K Hamilton, CK Cheng IEEE transactions on very large scale integration (VLSI) systems 19 (3), 520-524, 2009 | 9 | 2009 |
| Prediction of high-performance on-chip global interconnection Y Zhang, X Hu, A Deutsch, AE Engin, JF Buckwalter, CK Cheng Proceedings of the 11th international workshop on System level interconnect …, 2009 | 9 | 2009 |
| Performance and RLC crosstalk driven global routing L Zhang, T Jing, X Hong, J Xu, J Xiong, L He 2004 IEEE International Symposium on Circuits and Systems (ISCAS) 5, V-V, 2004 | 9 | 2004 |
| Analysis and Optimization of Low-Power Passive Equalizers for CPU–Memory Links L Zhang, W Yu, Y Zhang, R Wang, A Deutsch, GA Katopis, DM Dreps, ... IEEE Transactions on Components, Packaging and Manufacturing Technology 1 (9 …, 2011 | 7 | 2011 |
| Bus matrix synthesis based on steiner graphs for power efficient system-on-chip communications R Wang, Y Zhang, NC Chou, EFY Young, CK Cheng, R Graham IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2011 | 6 | 2011 |
| On-chip high performance signaling using passive compensation Y Zhang, L Zhang, A Tsuchiya, M Hashimoto, CK Cheng 2008 IEEE International Conference on Computer Design, 182-187, 2008 | 5 | 2008 |
| Clock skew analysis via vector fitting in frequency domain L Zhang, W Yu, H Zhu, W Zhang, CK Cheng 9th International Symposium on Quality Electronic Design (isqed 2008), 476-479, 2008 | 5 | 2008 |
Wenjian YuDept. Computer Science & Technology, Tsinghua UniversityVerified email at tsinghua.edu.cn
