Semiconductor integrated circuit device having a memory and an operational unit integrated therein T Matsumura, H Segawa, K Ishihara, S Uramoto, M Yoshimoto
US Patent 5,379,257, 1995
392 1995 A 100-MHz 2-D discrete cosine transform core processor S Uramoto, Y Inoue, A Takabatake, J Takeda, Y Yamashita, H Terane, ...
IEICE Transactions on Electronics 75 (4), 390-397, 1992
255 1992 A divided word-line structure in the static RAM and its application to a 64K full CMOS RAM M Yoshimoto, K Anami, H Shinohara, T Yoshihara, H Takagi, S Nagao, ...
IEEE Journal of Solid-State Circuits 18 (5), 479-485, 1983
245 1983 Architectural study of HOG feature extraction processor for real-time object detection K Mizuno, Y Terachi, K Takagi, S Izumi, H Kawaguchi, M Yoshimoto
2012 IEEE Workshop on Signal Processing Systems, 197-202, 2012
181 2012 An area-conscious low-voltage-oriented 8T-SRAM design under DVS environment Y Morita, H Fujiwara, H Noguchi, Y Iguchi, K Nii, H Kawaguchi, ...
2007 IEEE Symposium on VLSI Circuits, 256-257, 2007
181 2007 Sensor network system for acquiring high quality speech signals and communication method therefor H Kawaguchi, M Yoshimoto, S Izumi
US Patent 8,600,443, 2013
179 2013 Variable delay circuit for delaying input data H Kawai, M Yoshimoto
US Patent 4,953,128, 1990
164 1990 Digital delay unit with interleaved memory M Yoshimoto
US Patent 4,849,937, 1989
163 1989 Which is the best dual-port SRAM in 45-nm process technology?—8T, 10T single end, and 10T differential— H Noguchi, S Okumura, Y Iguchi, H Fujiwara, Y Morita, K Nii, ...
2008 IEEE International Conference on Integrated Circuit Design and …, 2008
143 2008 Read only memory for storing multi-data S Uramoto, T Matsumura, M Yoshimoto, K Ishihara, H Segawa
US Patent 5,394,355, 1995
94 1995 A 64Kb full CMOS RAM with divided word line structure M Yoshimoto, K Anami, H Shinohara, T Yoshihara, H Takagi, S Nagao, ...
1983 IEEE International Solid-State Circuits Conference. Digest of Technical …, 1983
86 1983 Radiation-induced reduction of osteoblast differentiation in C2C12 cells T Sakurai, Y Sawada, M Yoshimoto, M Kawai, J Miyakoshi
Journal of radiation research 48 (6), 515-521, 2007
84 2007 A 10T non-precharge two-port SRAM for 74% power reduction in video processing H Noguchi, Y Iguchi, H Fujiwara, Y Morita, K Nii, H Kawaguchi, ...
IEEE Computer Society Annual Symposium on VLSI (ISVLSI'07), 107-112, 2007
76 2007 A half-pel precision MPEG2 motion-estimation processor with concurrent three-vector search K Ishihara, S Masuda, S Hattori, H Nishikawa, Y Ajioka, T Yamada, ...
IEEE Journal of Solid-State Circuits 30 (12), 1502-1509, 1995
67 1995 Design consideration of a static memory cell K Anami, M Yoshimoto, H Shinohara, Y Hirata, T Nakano
IEEE journal of solid-state circuits 18 (4), 414-418, 1983
58 1983 Semiconductor memory device having three-transistor type memory cells structure without additional gates T Matsumura, M Yoshimoto
US Patent 4,935,896, 1990
57 1990 A Wearable Healthcare System With a 13.7 A Noise Tolerant ECG Processor S Izumi, K Yamashita, M Nakano, H Kawaguchi, H Kimura, K Marumoto, ...
IEEE Transactions on Biomedical Circuits and Systems 9 (5), 733-742, 2014
56 2014 Exposure to extremely low frequency magnetic fields affects insulin‐secreting cells T Sakurai, M Yoshimoto, S Koyama, J Miyakoshi
Bioelectromagnetics: Journal of the Bioelectromagnetics Society, The Society …, 2008
54 2008 A half-pel precision motion estimation processor for NTSC-resolution video S Uramoto, A Takabatake, M Suzuki, H Sakurai, M Yoshimoto
IEICE Transactions on Electronics 77 (12), 1930-1936, 1994
48 1994 Future technological and economic prospects for VLSI H Komiya, M Yoshimoto, H Ishikura
IEICE TRANSACTIONS on Electronics 76 (11), 1555-1563, 1993
47 1993