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Joonmoo Huh
Joonmoo Huh
Bestätigte E-Mail-Adresse bei intel.com
Titel
Zitiert von
Zitiert von
Jahr
Improving the effectiveness of searching for isomorphic chains in superword level parallelism
J Huh, J Tuck
Proceedings of the 50th Annual IEEE/ACM International Symposium on …, 2017
122017
Computing in 3D
P Franzon, E Rotenberg, J Tuck, WR Davis, H Zhou, J Schabel, Z Zhang, ...
2015 IEEE Custom Integrated Circuits Conference (CICC), 1-6, 2015
102015
Systems, apparatuses, and method for strided access
E Ould-Ahmed-Vall, S Sair, J Huh
US Patent 9,946,541, 2018
72018
Instruction and Logic for Permute with Out of Order Loading
E Ould-Ahmed-Vall, S Sair, J Huh
US Patent App. 14/975,390, 2017
42017
3D-enabled customizable embedded computer (3DECC)
PD Franzon, E Rotenberg, J Tuck, H Zhou, WR Davis, H Dai, J Huh, S Ku, ...
2014 International 3D Systems Integration Conference (3DIC), 1-3, 2014
42014
Instruction and Logic for Permute Sequence
E Ould-Ahmed-Vall, S Sair, J Huh
US Patent App. 14/975,380, 2017
22017
Applications and design styles for 3DIC
PD Franzon, E Rotenberg, J Tuck, WR Davis, H Zhou, J Schabel, Z Zhang, ...
2013 IEEE International Electron Devices Meeting, 29.4. 1-29.4. 4, 2013
22013
SSD-based RAID-6 System Architecture for Reliability and Performance Enhancement
JS Song, JM Huh, YS Yang, DH Kim
Journal of the Institute of Electronics Engineers of Korea CI 47 (6), 47-56, 2010
12010
Apparatuses, methods, and systems for instructions for aligning tiles of a matrix operations accelerator
E Ould-Ahmed-Vall, J Huh, K Krommydas, MF Amin
US Patent App. 17/134,136, 2022
2022
Instructions and logic for blend and permute operation sequences
E Ould-Ahmed-Vall, S Sair, J Huh
US Patent 10,152,321, 2018
2018
Using Runtime Value-range Invariants to Optimize The Bit Width of Data for Memory Usage Efficiency.
J Huh
2012
The performance comparison of Erasure Code to recover from chip units based on SSD
YS Yang, JM Huh, JS Song, DH Kim
Proceedings of the Korean Information Science Society Conference, 347-351, 2010
2010
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