| 5.8 a 3ghz 64b arm v8 processor in 40nm bulk cmos technology A Yeung, H Partovi, Q Harvard, L Ravezzi, J Ngai, R Homer, M Ashcraft, ... 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 28 | 2014 |
| Clock and synchronization networks for a 3 GHz 64 Bit ARMv8 8-core SoC L Ravezzi, H Partovi IEEE Journal of Solid-State Circuits 50 (7), 1702-1710, 2015 | 13 | 2015 |
| A scalable I/O architecture for wide I/O DRAM Q Harvard, RJ Baker 2011 IEEE 54th International Midwest Symposium on Circuits and Systems …, 2011 | 10 | 2011 |
| Wide I/O DRAM Architecture Utilizing Proximity Communication QIZ Harvard | 7 | 2009 |
| Clock and synchronization networks for a 3GHz 64bit ARMv8 8-core SoC L Ravezzi, H Partovi, D Wang, C Wang, R Cohen, M Ashcraft, A Yeung, ... ESSCIRC 2014-40th European Solid State Circuits Conference (ESSCIRC), 247-250, 2014 | 2 | 2014 |
| Main memory with proximity communication: A Wide I/O DRAM architecture Q Harvard, RJ Baker, R Drost 2010 IEEE Workshop on Microelectronics and Electron Devices, 1-4, 2010 | 2 | 2010 |
| Low-Power, High-Bandwidth and Ultra-Small Memory Module Design QIZ Harvard | 1 | 2011 |
| High frequency voltage supply monitor L Ravezzi, Q Harvard, H Partovi US Patent 9,568,511, 2017 | | 2017 |
| Increased DRAM-array throughput using inactive bitlines QI Harvard, RJ Drost, RJ Baker US Patent 8,395,947, 2013 | | 2013 |
| ISSCC 2014/SESSION 5/PROCESSORS/5.8 A Yeung, H Partovi, Q Harvard, L Ravezzi, J Ngai, R Homer, M Ashcraft, ... | | |
| Design for MOSIS Educational Program RJ Baker, Q Harvard | | |
| Nano-Memory Module Design Q Harvard, RJ Baker | | |
