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Hector Pettenghi
Hector Pettenghi
Professor Adjunto (UFSC)
Bestätigte E-Mail-Adresse bei eel.ufsc.br - Startseite
Titel
Zitiert von
Zitiert von
Jahr
RNS Reverse Converters for Moduli Sets With Dynamic Ranges up to-bit
H Pettenghi, R Chaves, L Sousa
IEEE Transactions on Circuits and Systems I: Regular Papers 60 (6), 1487-1500, 2012
582012
Multi-threshold threshold logic circuit design using resonant tunnelling devices
MJ Avedillo, JM Quintana, H Pettenghi, PM Kelly, CJ Thompson
Electronics Letters 39 (21), 1, 2003
582003
Using multi-threshold threshold gates in RTD-based logic design: A case study
H Pettenghi, MJ Avedillo, JM Quintana
Microelectronics Journal 39 (2), 241-247, 2008
382008
Increased logic functionality of clocked series-connected RTDs
MJ Avedillo, JM Quintana, HP Roldán
Nanotechnology, IEEE Transactions on 5 (5), 606-611, 2006
352006
Self-latching operation of MOBILE circuits using series-connection of RTDs and transistors
MJ Avedillo, JM Quintana, H Pettenghi
IEEE Transactions on Circuits and Systems II: Express Briefs 53 (5), 334-338, 2006
292006
Method to design general RNS reverse converters for extended moduli sets
H Pettenghi, R Chaves, L Sousa
IEEE Transactions on Circuits and Systems II: Express Briefs 60 (12), 877-881, 2013
272013
Efficient implementation of modular multiplication by constants applied to RNS reverse converters
R de Matos, R Paludo, N Chervyakov, PA Lyakhov, H Pettenghi
2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017
212017
RNS Arithmetic Units for Modulo {2^ n+-k}
PM Matutino, H Pettenghi, R Chaves, L Sousa
2012 15th Euromicro Conference on Digital System Design, 795-802, 2012
192012
Single phase clock scheme for MOBILE logic gates
H Pettenghi, MJ Avedillo, JM Quintana
Electronics Letters 42 (24), 1, 2006
192006
Improved nanopipelined RTD adder using generalized threshold gates
H Pettenghi, MJ Avedillo, JM Quintana
IEEE Transactions on Nanotechnology 10 (1), 155-162, 2009
182009
Operation limits for RTD-based MOBILE circuits
JM Quintana, MJ Avedillo, J Nunez, HP Roldán
IEEE Transactions on Circuits and Systems I: Regular Papers 56 (2), 350-363, 2008
172008
Logic models supporting the design of MOBILE-based RTD circuits
MJ Avedillo, JM Quintana, H Pettenghi
2005 IEEE International Conference on Application-Specific Systems …, 2005
172005
A novel contribution to the RTD-based threshold logic family
H Pettenghi, MJ Avedillo, JM Quintana
2008 IEEE International Symposium on Circuits and Systems (ISCAS), 2350-2353, 2008
142008
Useful logic blocks based on clocked series-connected RTDs
H Pettenghi, MJ Avedillo, JM Quintana
4th IEEE Conference on Nanotechnology, 2004., 593-595, 2004
102004
Efficient implementation of multi-moduli architectures for Binary-to-RNS conversion
H Pettenghi, L Sousa, JA Ambrose
17th Asia and South Pacific Design Automation Conference, 819-824, 2012
92012
DARNS: A randomized multi-modulo RNS architecture for double-and-add in ECC to prevent power analysis side channel attacks
JA Ambrose, H Pettenghi, L Sousa
2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 620-625, 2013
82013
Randomised multi‐modulo residue number system architecture for double‐and‐add to prevent power analysis side channel attacks
JA Ambrose, H Pettenghi, D Jayasinghe, L Sousa
IET Circuits, Devices & Systems 7 (5), 283-293, 2013
72013
Multiplierbased binary-to-RNS converter modulo {2n±k}
PM Matutino, H Pettenghi, R Chaves, L Sousa
Proc. 26th Conf. DCIS, 125-130, 2011
72011
RTD-based compact programmable gates
JM Quintana, MJ Avedillo, H Pettenghi
2004 IEEE International Joint Conference on Neural Networks (IEEE Cat. No …, 2004
72004
Programmable logic gate based on resonant tunnelling devices
JM Quintana, MJ Avedillo, H Pettenghi
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No …, 2004
72004
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