| An Efficient Methodology for Mapping Quantum Circuits to the IBM QX Architectures A Zulehner, A Paler, R Wille IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018 | 272 | 2018 |
| An efficient methodology for mapping quantum circuits to the IBM QX architectures A Zulehner, A Paler, R Wille IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 272 | 2018 |
| Encoding electronic spectra in quantum circuits with linear T complexity R Babbush, C Gidney, DW Berry, N Wiebe, J McClean, A Paler, A Fowler, ... Physical Review X 8 (4), 041015, 2018 | 189 | 2018 |
| Scalable service deployment on software-defined networks J Rubio-Loyola, A Galis, A Astorga, J Serrat, L Lefevre, A Fischer, A Paler, ... IEEE Communications Magazine 49 (12), 84-93, 2011 | 84 | 2011 |
| Fault-tolerant, high-level quantum circuits: form, compilation and description A Paler, I Polian, K Nemoto, SJ Devitt Quantum Science and Technology 2 (2), 025003, 2017 | 72* | 2017 |
| Skyrmion Logic System for Large-Scale Reversible Computation M Chauwin, X Hu, F Garcia-Sanchez, N Betrabet, A Paler, C Moutafis, ... Physical Review Applied 12 (6), 064053, 2019 | 58 | 2019 |
| Exponential suppression of bit or phase errors with cyclic error correction Z Chen, KJ Satzinger, J Atalaya, AN Korotkov, A Dunsworth, D Sank, ... Nature 595 (7867), 383-387, 2021 | 53 | 2021 |
| Removing leakage-induced correlated errors in superconducting quantum error correction M McEwen, D Kafri, Z Chen, J Atalaya, KJ Satzinger, C Quintana, ... Nature Communications 12 (1), 1-7, 2021 | 34 | 2021 |
| Mapping of topological quantum circuits to physical hardware A Paler, SJ Devitt, K Nemoto, I Polian Scientific reports 4 (1), 1-10, 2014 | 31 | 2014 |
| Synthesis of arbitrary quantum circuits to topological assembly A Paler, SJ Devitt, AG Fowler Scientific reports 6 (1), 1-16, 2016 | 29 | 2016 |
| On the Influence of Initial Qubit Placement During NISQ Circuit Compilation A Paler International Workshop on Quantum Technology and Optimization Problems, 207-217, 2019 | 27 | 2019 |
| Platforms and software systems for an autonomic internet J Rubio-Loyola, A Astorga, J Serrat, WK Chai, L Mamatas, A Galis, ... 2010 IEEE Global Telecommunications Conference GLOBECOM 2010, 1-6, 2010 | 24 | 2010 |
| NISQ circuit compilation is the travelling salesman problem on a torus A Paler, A Zulehner, R Wille Quantum Science and Technology 6 (2), 025016, 2021 | 22* | 2021 |
| Tomographic testing and validation of probabilistic circuits A Paler, A Alaghi, I Polian, JP Hayes 2011 Sixteenth IEEE European Test Symposium, 63-68, 2011 | 20 | 2011 |
| Parallelizing the queries in a bucket-brigade quantum random access memory A Paler, O Oumarou, R Basmadjian Physical Review A 102 (3), 032608, 2020 | 18* | 2020 |
| Synthesis of topological quantum circuits A Paler, S Devitt, K Nemoto, I Polian 2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH …, 2012 | 18 | 2012 |
| Synthesis of arbitrary quantum circuits to topological assembly: Systematic, online and compact A Paler, AG Fowler, R Wille Scientific reports 7 (1), 1-16, 2017 | 16 | 2017 |
| Detection and diagnosis of faulty quantum circuits A Paler, I Polian, JP Hayes 17th Asia and South Pacific Design Automation Conference, 181-186, 2012 | 16 | 2012 |
| Software-based pauli tracking in fault-tolerant quantum circuits A Paler, S Devitt, K Nemoto, I Polian 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-4, 2014 | 14 | 2014 |
| An introduction into fault-tolerant quantum computing A Paler, SJ Devitt Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015 | 12* | 2015 |
Simon DevittUniversity of Technology SydneyVerified email at uts.edu.au
