Alexandru Paler
Alexandru Paler
Verified email at jku.at
Title
Cited by
Cited by
Year
An Efficient Methodology for Mapping Quantum Circuits to the IBM QX Architectures
A Zulehner, A Paler, R Wille
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018
1662018
An efficient methodology for mapping quantum circuits to the IBM QX architectures
A Zulehner, A Paler, R Wille
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
1662018
Encoding electronic spectra in quantum circuits with linear T complexity
R Babbush, C Gidney, DW Berry, N Wiebe, J McClean, A Paler, A Fowler, ...
Physical Review X 8 (4), 041015, 2018
1192018
Scalable service deployment on software-defined networks
J Rubio-Loyola, A Galis, A Astorga, J Serrat, L Lefevre, A Fischer, A Paler, ...
IEEE Communications Magazine 49 (12), 84-93, 2011
792011
Fault-tolerant, high-level quantum circuits: form, compilation and description
A Paler, I Polian, K Nemoto, SJ Devitt
Quantum Science and Technology 2 (2), 025003, 2017
60*2017
Mapping of topological quantum circuits to physical hardware
A Paler, SJ Devitt, K Nemoto, I Polian
Scientific reports 4 (1), 1-10, 2014
272014
Platforms and software systems for an autonomic internet
J Rubio-Loyola, A Astorga, J Serrat, WK Chai, L Mamatas, A Galis, ...
2010 IEEE Global Telecommunications Conference GLOBECOM 2010, 1-6, 2010
242010
Synthesis of arbitrary quantum circuits to topological assembly
A Paler, SJ Devitt, AG Fowler
Scientific reports 6 (1), 1-16, 2016
232016
Skyrmion Logic System for Large-Scale Reversible Computation
M Chauwin, X Hu, F Garcia-Sanchez, N Betrabet, A Paler, C Moutafis, ...
Physical Review Applied 12 (6), 064053, 2019
212019
On the Influence of Initial Qubit Placement During NISQ Circuit Compilation
A Paler
International Workshop on Quantum Technology and Optimization Problems, 207-217, 2019
192019
Tomographic testing and validation of probabilistic circuits
A Paler, A Alaghi, I Polian, JP Hayes
2011 Sixteenth IEEE European Test Symposium, 63-68, 2011
172011
Synthesis of topological quantum circuits
A Paler, S Devitt, K Nemoto, I Polian
2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH …, 2012
162012
Synthesis of arbitrary quantum circuits to topological assembly: Systematic, online and compact
A Paler, AG Fowler, R Wille
Scientific reports 7 (1), 1-16, 2017
152017
Software-based pauli tracking in fault-tolerant quantum circuits
A Paler, S Devitt, K Nemoto, I Polian
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-4, 2014
152014
NISQ circuit compilation is the travelling salesman problem on a torus
A Paler, A Zulehner, R Wille
Quantum Science and Technology 6 (2), 025016, 2021
14*2021
Detection and diagnosis of faulty quantum circuits
A Paler, I Polian, JP Hayes
17th Asia and South Pacific Design Automation Conference, 181-186, 2012
132012
Approximate simulation of circuits with probabilistic behavior
A Paler, J Kinseher, I Polian, JP Hayes
2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2013
122013
Efficient mapping of quantum circuits to the IBM QX architectures. In 2018 Design, Automation Test in Europe Conference Exhibition (DATE)
A Zulehner, A Paler, R Wille
IEEE, 2018
112018
Design, Automation and Test in Europe Conference and Exhibition
A Paler, S Devitt, K Nemoto, I Polian
IEEE, 2014
102014
A fully fault-tolerant representation of quantum circuits
A Paler, I Polian, K Nemoto, SJ Devitt
International Conference on Reversible Computation, 139-154, 2015
92015
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