somnath paul
somnath paul
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Zitiert von
Zitiert von
MERO: A Statistical Approach for Hardware Trojan Detection
RS Chakraborty, F Wolff, S Paul, C Papachristou, S Bhunia
International Workshop on Cryptographic Hardware and Embedded Systems, 396-410, 2009
Hardware Trojan detection by multiple-parameter side-channel analysis
S Narasimhan, D Du, RS Chakraborty, S Paul, FG Wolff, CA Papachristou, ...
IEEE Transactions on computers 62 (11), 2183-2195, 2012
Event-driven random back-propagation: Enabling neuromorphic deep learning machines
EO Neftci, C Augustine, S Paul, G Detorakis
Frontiers in neuroscience 11, 324, 2017
Multiple-parameter side-channel analysis: A non-invasive hardware Trojan detection approach
S Narasimhan, D Du, RS Chakraborty, S Paul, F Wolff, C Papachristou, ...
2010 IEEE international symposium on hardware-oriented security and trust …, 2010
On-demand transparency for improving hardware Trojan detectability
RS Chakraborty, S Paul, S Bhunia
2008 IEEE International Workshop on Hardware-Oriented Security and Trust, 48-50, 2008
VIm-Scan: A low overhead scan design approach for protection of secret key in scan-based secure chips
S Paul, RS Chakraborty, S Bhunia
25th IEEE VLSI Test Symposium (VTS'07), 455-460, 2007
A fast hardware approach for approximate, efficient logarithm and antilogarithm computations
S Paul, N Jayakumar, SP Khatri
IEEE transactions on very large scale integration (vlsi) systems 17 (2), 269-277, 2008
iACT: A software-hardware framework for understanding the scope of approximate computing
AK Mishra, R Barik, S Paul
Workshop on Approximate Computing Across the System Stack (WACAS), 52, 2014
Reliability-driven ECC allocation for multiple bit error resilience in processor cache
S Paul, F Cai, X Zhang, S Bhunia
IEEE Transactions on Computers 60 (1), 20-34, 2010
A circuit and architecture codesign approach for a hybrid cmos–sttram nonvolatile fpga
S Paul, S Mukhopadhyay, S Bhunia
IEEE Transactions on Nanotechnology 10 (3), 385-394, 2010
Harvesting wasted heat in a microprocessor using thermoelectric generators: modeling, analysis and measurement
Y Zhou, S Paul, S Bhunia
2008 Design, Automation and Test in Europe, 98-103, 2008
A Sub-cm3 Energy-Harvesting Stacked Wireless Sensor Node Featuring a Near-Threshold Voltage IA-32 Microcontroller in 14-nm Tri-Gate CMOS for Always-ON Always-Sensing Applications
S Paul, V Honkote, RG Kim, T Majumder, PA Aseron, V Grossnickle, ...
IEEE Journal of Solid State Circuits 52 (4), 2017
A scalable memory-based reconfigurable computing framework for nanoscale crossbar
S Paul, S Bhunia
IEEE transactions on Nanotechnology 11 (3), 451-462, 2010
FPGA-based hardware acceleration for Boolean satisfiability
K Gulati, S Paul, SP Khatri, S Patil, A Jas
ACM Transactions on Design Automation of Electronic Systems (TODAES) 14 (2 …, 2009
Reconfigurable computing using content addressable memory for improved performance and resource usage
S Paul, S Bhunia
Proceedings of the 45th annual Design Automation Conference, 786-791, 2008
Hybrid CMOS-STTRAM non-volatile FPGA: Design challenges and optimization approaches
S Paul, S Mukhopadhyay, S Bhunia
2008 IEEE/ACM International Conference on Computer-Aided Design, 589-592, 2008
Miner. Defining the IEEE-854 floating-point standard in PVS
S Paul
NASA Technical Memorandum 110167, 1995
Fault-tolerant dynamic task mapping and scheduling for network-on-chip-based multicore platform
N Chatterjee, S Paul, S Chattopadhyay
ACM Transactions on Embedded Computing Systems (TECS) 16 (4), 1-24, 2017
Exploring spin transfer torque devices for unconventional computing
K Roy, D Fan, X Fong, Y Kim, M Sharad, S Paul, S Chatterjee, S Bhunia, ...
IEEE journal on Emerging and Selected Topics in Circuits and Systems 5 (1), 5-16, 2015
Task mapping and scheduling for network-on-chip based multi-core platform with transient faults
N Chatterjee, S Paul, S Chattopadhyay
Journal of Systems Architecture 83, 34-56, 2018
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