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Robert Margelli
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HL5: A 32-bit RISC-V Processor Designed with High-Level Synthesis
P Mantovani, R Margelli, D Giri, LP Carloni
2020 IEEE Custom Integrated Circuits Conference (CICC), 1-8, 2020
42020
System-level Design of a Latency-insensitive RISC-V Microprocessor and Optimization via High-level Synthesis
R Margelli, L Lavagno, L Carloni
Politecnico di Torino, 2017
22017
On the development of a high-level fault simulator for the analysis of performance faults on speculative modules
A Floridia, R Margelli, E Sánchez
2017 18th IEEE Latin American Test Symposium (LATS), 1-6, 2017
2017
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Articles 1–3