Massimo Alioto
Title
Cited by
Cited by
Year
Ultra-low power VLSI circuit design demystified and explained: A tutorial
M Alioto
IEEE Transactions on Circuits and Systems I: Regular Papers 59 (1), 3-29, 2012
3642012
Analysis and comparison on full adder block in submicron technology
M Alioto, G Palumbo
IEEE transactions on very large scale integration (VLSI) systems 10 (6), 806-823, 2002
2592002
Model and design of bipolar and MOS current-mode logic: CML, ECL and SCL digital circuits
M Alioto, G Palumbo
Springer Science & Business Media, 2006
1982006
Understanding the effect of process variations on the delay of static and domino logic
M Alioto, G Palumbo, M Pennisi
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18 (5), 697-710, 2009
1842009
Understanding DC behavior of subthreshold CMOS logic through closed-form analysis
M Alioto
IEEE Transactions on Circuits and Systems I: Regular Papers 57 (7), 1597-1607, 2010
1642010
Analysis and comparison in the energy-delay-area domain of nanometer CMOS flip-flops: Part I—Methodology and design strategies
M Alioto, E Consoli, G Palumbo
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19 (5), 725-736, 2010
160*2010
Enabling the Internet of Things: From Integrated Circuits to Integrated Systems
M Alioto
Springer, 2017
1372017
Leakage power analysis attacks: A novel class of attacks to nanometer cryptographic circuits
M Alioto, L Giancane, G Scotti, A Trifiletti
IEEE Transactions on Circuits and Systems I: Regular Papers 57 (2), 355-367, 2009
1242009
Design strategies for source coupled logic gates
M Alioto, G Palumbo
IEEE Transactions on Circuits and Systems I: Fundamental Theory and …, 2003
1182003
General strategies to design nanometer flip-flops in the energy-delay space
M Alioto, E Consoli, G Palumbo
IEEE Transactions on Circuits and Systems I: Regular Papers 57 (7), 1583-1596, 2009
1122009
Conditional push-pull pulsed latches with 726fJ· ps energy-delay product in 65nm CMOS
E Consoli, M Alioto, G Palumbo, J Rabaey
2012 IEEE International Solid-State Circuits Conference, 482-484, 2012
1012012
Leakage–delay tradeoff in FinFET logic circuits: A comparative analysis with bulk technology
M Agostinelli, M Alioto, D Esseni, L Selmi
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18 (2), 232-245, 2009
922009
A feedback strategy to improve the entropy of a chaos-based random bit generator
T Addabbo, M Alioto, A Fort, S Rocchi, V Vignoli
IEEE Transactions on Circuits and Systems I: Regular Papers 53 (2), 326-337, 2006
862006
A class of maximum-period nonlinear congruential generators derived from the Rényi chaotic map
T Addabbo, M Alioto, A Fort, A Pasini, S Rocchi, V Vignoli
IEEE Transactions on Circuits and Systems I: Regular Papers 54 (4), 816-828, 2007
842007
Flip-flop energy/performance versus clock slope and impact on the clock network design
M Alioto, E Consoli, G Palumbo
IEEE Transactions on Circuits and Systems I: Regular Papers 57 (6), 1273-1286, 2009
782009
14.3 15fJ/b static physically unclonable functions for secure chip identification with< 2% native bit instability and 140× Inter/Intra PUF hamming distance separation in 65nm
A Alvarez, W Zhao, M Alioto
2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015
772015
Impact of supply voltage variations on full adder delay: Analysis and comparison
M Alioto, G Palumbo
IEEE Transactions on very large scale integration (VLSI) systems 14 (12 …, 2006
772006
Comparative evaluation of layout density in 3T, 4T, and MT FinFET standard cells
M Alioto
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19 (5), 751-762, 2010
732010
Effectiveness of leakage power analysis attacks on DPA-resistant logic styles under process variations
M Alioto, S Bongiovanni, M Djukanovic, G Scotti, A Trifiletti
IEEE Transactions on Circuits and Systems I: Regular Papers 61 (2), 429-442, 2013
672013
Oscillation frequency in CML and ESCL ring oscillators
M Alioto, G Palumbo
IEEE Transactions on Circuits and Systems I: Fundamental Theory and …, 2001
652001
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Articles 1–20