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Enrico Reggiani
Enrico Reggiani
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On how to improve fpga-based systems design productivity via sdaccel
G Guidi, E Reggiani, L Di Tucci, G Durelli, M Blott, MD Santambrogio
2016 IEEE international parallel and distributed processing symposium …, 2016
402016
Vitruvius+: an area-efficient RISC-V decoupled vector coprocessor for high performance computing applications
F Minervini, O Palomar, O Unsal, E Reggiani, J Quiroga, J Marimon, ...
ACM Transactions on Architecture and Code Optimization 20 (2), 1-25, 2023
192023
Pareto optimal design space exploration for accelerated CNN on FPGA
E Reggiani, M Rabozzi, AM Nestorov, A Scolari, L Stornaiuolo, ...
2019 IEEE International Parallel and Distributed Processing Symposium …, 2019
192019
Enhancing the scalability of multi-fpga stencil computations via highly optimized hdl components
E Reggiani, E Del Sozzo, D Conficconi, G Natale, C Moroni, ...
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 14 (3), 1-33, 2021
132021
From exaflop to exaflow
T Becker, P Burovskiy, AM Nestorov, H Palikareva, E Reggiani, ...
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017
112017
Pearson Correlation Coefficient acceleration for modeling and mapping of neural interconnections
E Reggiani, E D’Arnese, A Purgato, MD Santambrogio
2017 IEEE International Parallel and Distributed Processing Symposium …, 2017
102017
A scalable dataflow implementation of curran's approximation algorithm
AM Nestorov, E Reggiani, H Palikareva, P Burovskiy, T Becker, ...
2017 IEEE international parallel and distributed processing symposium …, 2017
92017
An FPGA-based acceleration methodology and performance model for iterative stencils
E Reggiani, G Natale, C Moroni, MD Santambrogio
2018 IEEE International Parallel and Distributed Processing Symposium …, 2018
62018
Adaptable register file organization for vector processors
CR Lazo, E Reggiani, CR Morales, RF Bagué, LAV Vargas, MAR Salinas, ...
2022 IEEE International Symposium on High-Performance Computer Architecture …, 2022
52022
DVINO: A RISC-V Vector Processor Implemented in 65nm Technology
G Cabo, G Candón, X Carril, M Doblas, M Domínguez, A González, ...
2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS), 1-6, 2022
42022
Performance portable fpga design
N Voss, T Becker, S Tilbury, G Gaydadjiev, O Mencer, AM Nestorov, ...
Proceedings of the 2020 ACM/SIGDA International Symposium on Field …, 2020
42020
Mix-GEMM: An efficient HW-SW Architecture for Mixed-Precision Quantized Deep Neural Networks Inference on Edge Devices
E Reggiani, A Pappalardo, M Doblas, M Moreto, M Olivieri, OS Unsal, ...
2023 IEEE International Symposium on High-Performance Computer Architecture …, 2023
32023
Bison-e: A lightweight and high-performance accelerator for narrow integer linear algebra computing on the edge
E Reggiani, CR Lazo, RF Bagué, A Cristal, M Olivieri, OS Unsal
Proceedings of the 27th ACM International Conference on Architectural …, 2022
32022
A case study for an accelerated dcnn on fpga-based embedded distributed system
AM Nestorov, A Scolari, E Reggiani, L Stornaiuolo, MD Santambrogio
2019 IEEE International Parallel and Distributed Processing Symposium …, 2019
32019
Flex-SFU: Accelerating DNN Activation Functions by Non-Uniform Piecewise Approximation
E Reggiani, R Andri, L Cavigelli
arXiv preprint arXiv:2305.04546, 2023
22023
Sargantana: An Academic SoC RISC-V Processor in 22nm FDSOI Technology
M Doblas, G Candón, X Carril, M Domínguez, E Erra, A González, ...
2023 38th Conference on Design of Circuits and Integrated Systems (DCIS), 1-6, 2023
2023
DVINO: A RISC-V vector processor implemented in 65nm technology
G Cabo Pitarch, G Candon, X Carril, M Doblas Font, ...
DCIS 2022: proceedings of the 37th Conference on Design of Circuits and …, 2022
2022
GPU-based computation for brain spatio-temporal networks definition
A Purgato, E Reggiani, E D'Arnese, T Berger-Wolf, M Grimaldi, G Durelli, ...
2017 39th Annual International Conference of the IEEE Engineering in …, 2017
2017
Improving the scalability of multi-FPGA stencil computations through highly customizable HDL templates
E REGGIANI
Politecnico di Milano, 2017
2017
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Articles 1–19