| CC-SPRA: Correlation Coefficients Approach for Signal Probability-Based Reliability Analysis H Jahanirad IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2019 | 30 | 2019 |
| Broadband class-E power amplifier design using tunable output matching network F Moloudi, H Jahanirad AEU-International Journal of Electronics and Communications 118, 153142, 2020 | 23 | 2020 |
| BIST-based Testing and Diagnosis of LUTs in SRAM-based FPGAs H Jahanirad, H Karam Emerging Science Journal 1 (4), 216-225, 2017 | 20 | 2017 |
| NN-SSTA: A deep neural network approach for statistical static timing analysis MA Savari, H Jahanirad Expert Systems with Applications 149, 113309, 2020 | 16 | 2020 |
| Efficient reliability evaluation of combinational and sequential logic circuits H Jahanirad Journal of Computational Electronics, 1-13, 2019 | 16 | 2019 |
| Fast reliability analysis method for sequential logic circuits K Mohammadi, H Jahanirad, P Attarsharghi 2011 21st International Conference on Systems Engineering, 352-356, 2011 | 14 | 2011 |
| SEQUENTIAL LOGIC CIRCUITS RELIABILITY ANALYSIS H Jahanirad, K Mohammadi Journal of Circuits, Systems, and Computers 21 (05), 1250040, 2012 | 10 | 2012 |
| Reliable Implementation on SRAM-based FPGA using Evolutionary Methods. H Jahanirad, K Mohammadi IETE Journal of Research (Taylor & Francis) 59 (5), 2013 | 9 | 2013 |
| FPGA-based implementation of deep neural network using stochastic computing M Nobari, H Jahanirad Applied Soft Computing 137, 110166, 2023 | 8 | 2023 |
| Hardware acceleration of YOLOv7-tiny using high-level synthesis tools A Hosseiny, H Jahanirad Journal of Real-Time Image Processing 20 (4), 75, 2023 | 7 | 2023 |
| A concurrent BIST architecture for combinational logic circuits A Menbari, H Jahanirad 2020 10th International Conference on Computer and Knowledge Engineering …, 2020 | 6 | 2020 |
| An evolutionary approach to implement logic circuits on three dimensional FPGAs H Rahimi, H Jahanirad Expert Systems with Applications 174, 114780, 2021 | 5 | 2021 |
| Single fault reliability analysis in FPGA implemented circuits H Jahanirad, K Mohammadi, P Attarsharghi Thirteenth International Symposium on Quality Electronic Design (ISQED), 49-56, 2012 | 5 | 2012 |
| BIST-based online test approach for SRAM-based FPGAs H Jahanirad, H Karam Electrical Engineering (ICEE), Iranian Conference on, 178-183, 2018 | 4 | 2018 |
| Highly efficient implementation of chaotic systems utilizing high-level synthesis tools M Vaziri, H Jahanirad 2022 30th International Conference on Electrical Engineering (ICEE), 501-506, 2022 | 3 | 2022 |
| An efficient reliability estimation method for CNTFET‐based logic circuits H Jahanirad, M Hosseini ETRI Journal, 2021 | 3 | 2021 |
| A fast approach for deep neural network implementation on FPGA M Nobari, H Jahanirad 2021 29th Iranian Conference on Electrical Engineering (ICEE), 89-93, 2021 | 3 | 2021 |
| Reliability Estimation of Logic Circuits at the Transistor Level H Jahanirad Circuits, Systems, and Signal Processing, 2507–2534, 2021 | 3 | 2021 |
| Co-evolutionary Approach to Reduce Soft Error Rate of Implemented Circuits on SRAM_based FPGA H Jahanirad International Journal of Computer Applications 180 (43), 42-49, 2018 | 3 | 2018 |
| Reliability Model for Multiple-Error Protected Static Memories H Jahanirad Journal of Electronic Testing Theory and Applications 33 (2), 189-207, 2017 | 3 | 2017 |
Ahmad MenbariMaster of Science student, University of KurdistanVerified email at uok.ac.ir
