Sotirios Xydis
Cited by
Cited by
ECG signal analysis and arrhythmia detection on IoT wearable medical devices
D Azariadi, V Tsoutsouras, S Xydis, D Soudris
2016 5th International conference on modern circuits and systems …, 2016
Computation offloading and resource allocation for low-power IoT edge devices
F Samie, V Tsoutsouras, L Bauer, S Xydis, D Soudris, J Henkel
2016 IEEE 3rd World Forum on Internet of Things (WF-IoT), 7-12, 2016
Design-efficient approximate multiplication circuits through partial product perforation
G Zervakis, K Tsoumanis, S Xydis, D Soudris, K Pekmestzi
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (10 …, 2016
An optimized modified booth recoder for efficient design of the add-multiply operator
K Tsoumanis, S Xydis, C Efstathiou, N Moschopoulos, K Pekmestzi
IEEE Transactions on Circuits and Systems I: Regular Papers 61 (4), 1133-1143, 2014
SPIRIT: spectral-aware pareto iterative refinement optimization for supervised high-level synthesis
S Xydis, G Palermo, V Zaccaria, C Silvano
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014
High performance and area efficient flexible DSP datapath synthesis
S Xydis, G Economakos, D Soudris, K Pekmestzi
IEEE transactions on very large scale integration (VLSI) systems 19 (3), 429-442, 2009
Distributed QoS management for Internet of Things under resource constraints
F Samie, V Tsoutsouras, S Xydis, L Bauer, D Soudris, J Henkel
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on …, 2016
Designing coarse-grain reconfigurable architectures by inlining flexibility into custom arithmetic data-paths
S Xydis, G Economakos, K Pekmestzi
Integration 42 (4), 486-503, 2009
Walking through the energy-error Pareto frontier of approximate multipliers
V Leon, G Zervakis, S Xydis, D Soudris, K Pekmestzi
IEEE Micro 38 (4), 40-49, 2018
Custom multi-threaded dynamic memory management for multiprocessor system-on-chip platforms
S Xydis, A Bartzas, I Anagnostopoulos, D Soudris, K Pekmestzi
2010 International Conference on Embedded Computer Systems: Architectures …, 2010
Voltage island management in near threshold manycore architectures to mitigate dark silicon
C Silvano, G Palermo, S Xydis, I Stamelakos
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014
Cooperative arithmetic-aware approximation techniques for energy-efficient multipliers
V Leon, K Asimakopoulos, S Xydis, D Soudris, K Pekmestzi
Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019
An exploration framework for efficient high-level synthesis of support vector machines: Case study on ecg arrhythmia detection for xilinx zynq soc
V Tsoutsouras, K Koliogeorgi, S Xydis, D Soudris
Journal of Signal Processing Systems 88 (2), 127-147, 2017
2PARMA: parallel paradigms and run-time management techniques for many-core architectures
C Silvano, W Fornaciari, SC Reghizzi, G Agosta, G Palermo, V Zaccaria, ...
VLSI 2010 Annual Symposium, 65-79, 2011
Flexible datapath synthesis through arithmetically optimized operation chaining
S Xydis, I Triantafyllou, G Economakos, K Pekmestzi
2009 NASA/ESA Conference on Adaptive Hardware and Systems, 407-414, 2009
Custom microcoded dynamic memory management for distributed on-chip memory organizations
I Anagnostopoulos, S Xydis, A Bartzas, Z Lu, D Soudris, A Jantsch
IEEE Embedded Systems Letters 3 (2), 66-69, 2011
Hybrid approximate multiplier architectures for improved power-accuracy trade-offs
G Zervakis, S Xydis, K Tsoumanis, D Soudris, K Pekmestzi
2015 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2015
Dynamic memory management in vivado-hls for scalable many-accelerator architectures
D Diamantopoulos, S Xydis, K Siozios, D Soudris
International Symposium on Applied Reconfigurable Computing, 117-128, 2015
A framework for compiler level statistical analysis over customized vliw architecture
AH Ashouri, V Zaccaria, S Xydis, G Palermo, C Silvano
2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration …, 2013
Approximate multiplier architectures through partial product perforation: Power-area tradeoffs analysis
G Zervakis, K Tsoumanis, S Xydis, N Axelos, K Pekmestzi
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, 229-232, 2015
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