| A 20mW 61dB SNDR (60MHz BW) 1b 3rd-order continuous-time delta-sigma modulator clocked at 6GHz in 45nm CMOS V Srinivasan, V Wang, P Satarzadeh, B Haroun, M Corsi 2012 IEEE International Solid-State Circuits Conference, 158-160, 2012 | 112 | 2012 |
| Physical and filter pinna models based on anthropometry VR Algazi, RO Duda, P Satarzadeh Audio Engineering Society Convention 122, 2007 | 93 | 2007 |
| Adaptive semiblind calibration of bandwidth mismatch for two-channel time-interleaved ADCs P Satarzadeh, BC Levy, PJ Hurst IEEE Transactions on Circuits and Systems I: Regular Papers 56 (9), 2075-2088, 2008 | 76 | 2008 |
| Equalizer design and performance trade-offs in ADC-based serial links J Kim, EH Chen, J Ren, BS Leibowitz, P Satarzadeh, JL Zerbe, CKK Yang IEEE Transactions on Circuits and Systems I: Regular Papers 58 (9), 2096-2107, 2011 | 52 | 2011 |
| Bandwidth mismatch correction for a two-channel time-interleaved A/D converter P Satarzadeh, BC Levy, PJ Hurst 2007 IEEE International Symposium on Circuits and Systems, 1705-1708, 2007 | 40 | 2007 |
| A 5 Gb/s link with matched source synchronous and common-mode clocking techniques J Zerbe, B Daly, L Luo, W Stonecypher, W Dettloff, JC Eble, T Stone, ... IEEE Journal of Solid-State Circuits 46 (4), 974-985, 2011 | 34 | 2011 |
| A study of physical and circuit models of the human pinnae P Satarzadeh University of California, Davis, 2006 | 22 | 2006 |
| A parametric polyphase domain approach to blind calibration of timing mismatches for M-channel time-interleaved ADCs P Satarzadeh, BC Levy, PJ Hurst Proceedings of 2010 IEEE International Symposium on Circuits and Systems …, 2010 | 20 | 2010 |
| Method for calibrating a pipelined continuous-time sigma delta modulator P Satarzadeh, V Srinivasan, C Sestok US Patent 8,253,611, 2012 | 19 | 2012 |
| Pipelined continuous-time sigma delta modulator BS Haroun, V Srinivasan, P Satarzadeh, M Corsi US Patent 8,284,085, 2012 | 18 | 2012 |
| Digital calibration of a nonlinear S/H P Satarzadeh, BC Levy, PJ Hurst IEEE Journal of Selected Topics in Signal Processing 3 (3), 454-471, 2009 | 17 | 2009 |
| Pipelined ADC inter-stage error calibration K Shi, C Sestok, P Satarzadeh, AJ Redfern US Patent 8,451,152, 2013 | 15 | 2013 |
| Circuits for and methods of receiving data in an integrated circuit H Zhang, G Zhang, P Satarzadeh, ZD Wu US Patent 9,237,047, 2016 | 10 | 2016 |
| Excess loop delay compensation for a continuous time sigma delta modulator V Srinivasan, P Satarzadeh, VW Limetkai, B Haroun, M Corsi US Patent 8,514,117, 2013 | 9 | 2013 |
| Compressive sensing analog-to-digital converters P Satarzadeh, M Corsi, V Wang, AJ Redfern, F Mujica, C Sestok, K Shi, ... US Patent 8,390,490, 2013 | 9 | 2013 |
| Channel adaptive receiver switchable from a digital-based receiver mode to an analog-based receiver mode P Satarzadeh, H Zhang, G Zhang, ZD Wu US Patent 9,178,552, 2015 | 7 | 2015 |
| Digital correction of time interleaved DAC mismatches G Hovakimyan, P Hojabri, GA Martin, P Satarzadeh 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2019 | 6 | 2019 |
| Signal loss detector H Zhang, G Zhang, Y Xu, P Satarzadeh, ZD Wu US Patent 9,882,795, 2018 | 5 | 2018 |
| Method for calbrating a pipelined continuous-time sigma delta modulator P Satarzadeh, V Srinivasan, C Sestok US Patent 8,941,517, 2015 | 4 | 2015 |
| Method and apparatus for performing data conversion with non-uniform quantization AJ Redfern, P Satarzadeh US Patent 8,441,380, 2013 | 3 | 2013 |
Baher HarounTexas Instruments Senior Fellow, FIEEEVerified email at ti.com
