| On acceleration of SAT-based ATPG for industrial designs R Drechsler, S Eggersgluss, G Fey, A Glowatz, F Hapke, J Schlöffel, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2008 | 126 | 2008 |
| Improved SAT-based ATPG: More constraints, better compaction S Eggersglüß, R Wille, R Drechsler 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 85-90, 2013 | 72 | 2013 |
| Test pattern generation using Boolean proof engines R Drechsler, S Eggersglüß, G Fey, D Tille Springer Science & Business Media, 2009 | 71 | 2009 |
| SWORD: A SAT like prover using word level information R Wille, G Fey, D Große, S Eggersglüß, R Drechsler VLSI-SoC: Advanced Topics on Systems on a Chip, 1-17, 2009 | 70 | 2009 |
| A new SAT-based ATPG for generating highly compacted test sets S Eggersglüß, R Krenz-Bååth, A Glowatz, F Hapke, R Drechsler 2012 IEEE 15th International Symposium on Design and Diagnostics of …, 2012 | 33 | 2012 |
| High Quality Test Pattern Generation and Boolean Satisfiability S Eggersglüß, R Drechsler Springer Science & Business Media, 2012 | 32 | 2012 |
| Approximation-aware testing for approximate circuits A Chandrasekharan, S Eggersglüß, D Große, R Drechsler 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), 239-244, 2018 | 31 | 2018 |
| As-Robust-As-Possible test generation in the presence of small delay defects using pseudo-Boolean optimization S Eggersglüß, R Drechsler Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011, 1-6, 2011 | 31 | 2011 |
| Improving test pattern compactness in SAT-based ATPG S Eggersgluss, R Drechsler Asian Test Symposium, 2007. ATS'07. 16th, 445-452, 2007 | 31 | 2007 |
| On optimization-based ATPG and its application for highly compacted test sets S Eggersglüß, K Schmitz, R Krenz-Bååth, R Drechsler IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2016 | 28 | 2016 |
| Efficient data structures and methodologies for SAT-based ATPG providing high fault coverage in industrial application S Eggersglüß, R Drechsler Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions …, 2011 | 27 | 2011 |
| Robust timing-aware test generation using pseudo-boolean optimization S Eggersglüß, M Yilmaz, K Chakrabarty 2012 IEEE 21st Asian Test Symposium, 290-295, 2012 | 25 | 2012 |
| Incremental solving techniques for SAT-based ATPG D Tille, S Eggersgluss, R Drechsler IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010 | 24 | 2010 |
| MONSOON: SAT-based ATPG for path delay faults using multiple-valued logics S Eggersglüß, G Fey, A Glowatz, F Hapke, J Schloeffel, R Drechsler Journal of Electronic Testing 26 (3), 307-322, 2010 | 24 | 2010 |
| Optimization-based multiple target test generation for highly compacted test sets S Eggersglüß, K Schmitz, R Krenz-Baath, R Drechsler Test Symposium (ETS), 2014 19th IEEE European, 1-6, 2014 | 23 | 2014 |
| Robust algorithms for high quality test pattern generation using Boolean satisfiability S Eggersglüß, R Drechsler 2010 IEEE International Test Conference, 1-10, 2010 | 21 | 2010 |
| On Reduction of Deterministic Test Pattern Sets S Eggersglüß, S Milewski, J Rajski, J Tyszer 2021 IEEE International Test Conference (ITC), 260-267, 2021 | 19 | 2021 |
| Machine Learning-based Prediction of Test Power H Dhotre, S Eggersglüß, K Chakrabarty, R Drechsler 2019 IEEE European Test Symposium (ETS), 1-6, 2019 | 19 | 2019 |
| Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test S Eggersglüß, S Holst, D Tille, K Miyase, X Wen Asian Test Symposium (ATS), 2016 IEEE 25th, 173-178, 2016 | 19 | 2016 |
| Speeding up SAT-based ATPG using dynamic clause activation S Eggersgluss, D Tille, R Drechsler Asian Test Symposium, 2009. ATS'09., 177-182, 2009 | 19 | 2009 |
