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Rolf Ernst
Rolf Ernst
Professor at Institute of Computer and Network Engineering, TU Braunschweig, Germany
Verified email at tu-bs.de - Homepage
Title
Cited by
Cited by
Year
Hardware-software cosynthesis for microcontrollers
R Ernst, J Henkel, T Benner
IEEE Design & Test of computers 10 (4), 64-75, 1993
9681993
Hardware/software co-design
G De Michell, RK Gupta
Proceedings of the IEEE 85 (3), 349-365, 1997
844*1997
System level performance analysis–the SymTA/S approach
R Henia, A Hamann, M Jersak, R Racu, K Richter, R Ernst
IEE Proceedings-Computers and Digital Techniques 152 (2), 148-166, 2005
6162005
Codesign of embedded systems: Status and trends
R Ernst
IEEE Design & Test of Computers 15 (2), 45-54, 1998
2641998
Readings in hardware/software co-design
G De Micheli, R Ernst, W Wolf
Morgan Kaufmann, 2002
2612002
A formal approach to MpSoC performance verification
K Richter, M Jersak, R Ernst
Computer 36 (4), 60-67, 2003
1962003
An approach to automated hardware/software partitioning using a flexible granularity that is driven by high-level estimation techniques
J Henkel, R Ernst
IEEE transactions on very large scale integration (VLSI) systems 9 (2), 273-289, 2001
1852001
Embedded program timing analysis based on path clustering and architecture classification
R Ernst, W Ye
iccad 97, 1997
1681997
Scheduling analysis of real-time systems with precise modeling of cache related preemption delay
J Staschulat, S Schliecker, R Ernst
17th Euromicro Conference on Real-Time Systems (ECRTS'05), 41-48, 2005
1532005
Building timing predictable embedded systems
P Axer, R Ernst, H Falk, A Girault, D Grund, N Guan, B Jonsson, ...
ACM Transactions on Embedded Computing Systems (TECS) 13 (4), 1-37, 2014
1402014
Mixed criticality systems—a history of misconceptions?
R Ernst, M Di Natale
IEEE Design & Test 33 (5), 65-74, 2016
1192016
Hardware-software codesign of embedded controllers based on hardware extraction
R Ernst
The First International Workshop on Hardware-Software Codesign, 1992
1171992
A hardware/software partitioner using a dynamically determined granularity
J Henkel, R Ernst
Proceedings of the 34th annual Design Automation Conference, 691-696, 1997
1151997
Event model interfaces for heterogeneous system analysis
K Richter, R Ernst
Proceedings 2002 Design, Automation and Test in Europe Conference and …, 2002
1112002
Design and architectures for dependable embedded systems
J Henkel, L Bauer, J Becker, O Bringmann, U Brinkschulte, S Chakraborty, ...
Proceedings of the seventh IEEE/ACM/IFIP international conference on …, 2011
1092011
Formal worst-case timing analysis of Ethernet topologies with strict-priority and AVB switching
J Diemer, D Thiele, R Ernst
7th IEEE International Symposium on Industrial Embedded Systems (SIES'12), 1-10, 2012
1072012
Bounding the shared resource load for the performance analysis of multiprocessor systems
S Schliecker, M Negrean, R Ernst
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010
992010
FunState-an internal design representation for codesign
K Strehl, L Thiele, M Gries, D Ziegenbein, R Ernst, J Teich
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9 (4), 524-544, 2001
972001
Fast timing analysis for hardware-software co-synthesis
W Ye, R Ernst, T Benner, J Henkel
Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93 …, 1993
931993
Formal worst-case timing analysis of Ethernet TSN's time-aware and peristaltic shapers
D Thiele, R Ernst, J Diemer
2015 IEEE Vehicular Networking Conference (VNC), 251-258, 2015
892015
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