Magnetic memory device and magnetic substrate T Kunikiyo, K Eikyu, S Maeda US Patent 6,567,299, 2003 | 81 | 2003 |
A quantitative analysis of time-decay reproducible stress-induced leakage current in SiO/sub 2/films K Sakakibara, N Ajika, K Eikyu, K Ishikawa, H Miyoshi IEEE Transactions on Electron Devices 44 (6), 1002-1008, 1997 | 80 | 1997 |
Magnetic memory device capable of passing bidirectional currents through the bit lines T Kunikiyo, K Eikyu US Patent 6,950,369, 2005 | 64 | 2005 |
Application of a statistical compact model for random telegraph noise to scaled-SRAM Vmin analysis M Tanizawa, S Ohbayashi, T Okagaki, K Sonoda, K Eikyu, Y Hirano, ... 2010 Symposium on VLSI Technology, 95-96, 2010 | 54 | 2010 |
On the scaling limit of the Si-IGBTs with very narrow mesa structure K Eikyu, A Sakai, H Matsuura, Y Nakazawa, Y Akiyama, Y Yamaguchi, ... 2016 28th International Symposium on Power Semiconductor Devices and ICs …, 2016 | 39 | 2016 |
Magnetic memory device and magnetic substrate T Kunikiyo, K Eikyu, S Maeda US Patent 6,741,495, 2004 | 29 | 2004 |
80 nm CMOSFET technology using double offset-implanted source/drain extension and low temperature SiN process H Sayama, Y Nishida, H Oda, J Tsuchimoto, H Umeda, A Teramoto, ... International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No …, 2000 | 27 | 2000 |
70 nm SOI-CMOS of 135 GHz fmax with dual offset-implanted source-drain extension structure for RF/analog and logic applications T Matsumoto, S Maeda, K Ota, Y Hirano, K Eikyu, H Sayama, T Iwamatsu, ... Technical Digest-International Electron Devices Meeting, 219-222, 2001 | 23 | 2001 |
Semiconductor device and capacitance measurement method K Yamashita, H Umimoto, M Kobayashi, K Ohtani, T Kunikiyo, K Eikyu US Patent 6,894,520, 2005 | 22 | 2005 |
Advanced shallow trench isolation to suppress the inverse narrow channel effects for 0.24/spl mu/m pitch isolation and beyond K Horita, T Kuroi, Y Itoh, K Shiozawa, K Eikyu, K Goto, Y Inoue, M Inuishi 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No …, 2000 | 22 | 2000 |
Test structure measuring inter-and intralayer coupling capacitance of interconnection with subfemtofarad resolution T Kunikiyo, T Watanabe, T Kanamoto, H Asazato, M Shirota, K Eikyu, ... IEEE Transactions on Electron Devices 51 (5), 726-735, 2004 | 20 | 2004 |
Semiconductor device with lightly doped drain layer K Eikyu, Y Nishida US Patent 6,576,965, 2003 | 16 | 2003 |
Method of manufacturing semiconductor device Y Nishida, T Hayashi, T Yamashita, K Horita, K Eikyu US Patent App. 11/939,941, 2008 | 13 | 2008 |
Semiconductor device and method of checking semiconductor storage device T Kunikiyo, K Eikyu, K Yamashita, K Ohtani, H Umimoto, M Kobayashi US Patent 6,876,208, 2005 | 12 | 2005 |
Clarification of floating-body effects on drive current and short channel effect in deep sub-0.25/spl mu/m partially depleted SOI MOSFETs T Matsumoto, S Maeda, Y Hirano, K Eikyu, Y Yamaguchi, S Maegawa, ... IEEE Transactions on Electron Devices 49 (1), 55-60, 2002 | 12 | 2002 |
A Robust SOI SRAM Architecture by using Advanced ABC technology for 32nm node and beyond LSTP devices Y Hirano, M Tsujiuchi, K Ishikawa, H Shinohara, T Terada, Y Maki, ... 2007 IEEE Symposium on VLSI Technology, 78-79, 2007 | 10 | 2007 |
Method of simulating semiconductor manufacture with process functions according to user application T Kunikiyo, K Eikyu, K Sonoda, M Fujinaga, K Ishikawa, N Kotani US Patent 5,845,105, 1998 | 10 | 1998 |
Imaging device A Sakai, K Eikyu US Patent 9,755,094, 2017 | 9 | 2017 |
Analytical Approach for Enhancement of n-Channel Metal–Oxide–Semiconductor Field-Effect Transistor Performance with Carbon-Doped Source/Drain Formed by Molecular Carbon Ion … T Yamaguchi, Y Kawasaki, T Yamashita, N Miura, M Mizuo, J Tsuchimoto, ... Japanese journal of applied physics 50 (4S), 04DA02, 2011 | 9 | 2011 |
Semiconductor device with an STI structure which is capable of suppressing inverse narrow channel effect, and method of manufacturing the same K Eikyu US Patent App. 10/748,199, 2004 | 9 | 2004 |