Muhammad Yasin
Muhammad Yasin
Postdoctoral Researcher, SETH Lab, Texas A&M University
Verified email at nyu.edu - Homepage
Title
Cited by
Cited by
Year
SARLock: SAT attack resistant logic locking
M Yasin, B Mazumdar, JJV Rajendran, O Sinanoglu
2016 IEEE International Symposium on Hardware Oriented Security and Trust …, 2016
2542016
On Improving the Security of Logic Locking
M Yasin, J Rajendran, O Sinanoglu, R Karri
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2015
2082015
Provably-Secure Logic Locking: From Theory To Practice
M Yasin, A Sengupta, M Nabeel, M Ashraf, JJV Rajendran, O Sinanoglu
ACM SIGSAC Conference on Computer and Communications Security, 1601-1618, 2017
1822017
Removal Attacks on Logic Locking and Camouflaging Techniques
M Yasin, B Mazumdar, O Sinanoglu, J Rajendran
IEEE Transactions on Emerging Topics in Computing, 2017
1362017
Security Analysis of Anti-SAT
M Yasin, B Mazumdar, O Sinanoglu, J Rajendran
1242016
What to Lock?: Functional and Parametric Locking
M Yasin, A Sengupta, BC Schafer, Y Makris, O Sinanoglu, JJV Rajendran
Proceedings of the on Great Lakes Symposium on VLSI 2017, 351-356, 2017
762017
CamoPerturb: secure IC camouflaging for minterm protection
M Yasin, B Mazumdar, O Sinanoglu, J Rajendran
Proceedings of the 35th International Conference on Computer-Aided Design, 29, 2016
722016
Activation of logic encrypted chips: Pre-test or post-test?
M Yasin, SM Saeed, J Rajendran, O Sinanoglu
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 139-144, 2016
562016
Ultra-Low Power, Secure IoT Platform for Predicting Cardiovascular Diseases
M Yasin, T Tekeste, H Saleh, B Mohammad, O Sinanoglu, M Ismail
IEEE Transactions on Circuits and Systems I: Regular Papers 64 (9), 2624-2637, 2017
472017
ATPG-based cost-effective, secure logic locking
A Sengupta, M Nabeel, M Yasin, O Sinanoglu
2018 IEEE 36th VLSI Test Symposium (VTS), 1-6, 2018
442018
Security analysis of logic encryption against the most effective side-channel attack: DPA
M Yasin, B Mazumdar, SS Ali, O Sinanoglu
2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2015
362015
Transforming between logic locking and IC camouflaging
M Yasin, O Sinanoglu
2015 10th International Design & Test Symposium (IDT), 1-4, 2015
312015
Evolution of logic locking
M Yasin, O Sinanoglu
2017 IFIP/IEEE International Conference on Very Large Scale Integration …, 2017
282017
Image based vehicle type identification
U Iqbal, SW Zamir, MH Shahid, K Parwaiz, M Yasin, MS Sarfraz
2010 International Conference on Information and Emerging Technologies, 1-5, 2010
272010
ScanSAT: unlocking obfuscated scan chains
L Alrahis, M Yasin, H Saleh, B Mohammad, M Al-Qutayri, O Sinanoglu
Proceedings of the 24th Asia and South Pacific Design Automation Conference …, 2019
252019
Testing the Trustworthiness of IC Testing: An Oracle-less Attack on IC Camouflaging
M Yasin, O Sinanoglu, J Rajendran
IEEE Transactions on Information Forensics and Security 12 (11), 2668-2682, 2017
252017
MixLock: Securing mixed-signal circuits via logic locking
J Leonhard, M Yasin, S Turk, M Nabeel, MM Louërat, R Chotin-Avot, ...
Design, Automation and Test in Europe (DATE 2019), 84-89, 2019
182019
TTLock: Tenacious and traceless logic locking
M Yasin, B Mazumdar, JJV Rajendran, O Sinanoglu
2017 IEEE International Symposium on Hardware Oriented Security and Trust …, 2017
182017
Keynote: A Disquisition on Logic Locking
A Chakraborty, NG Jayasankaran, Y Liu, J Rajendran, O Sinanoglu, ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019
172019
Functional Reverse Engineering on SAT-Attack Resilient Logic Locking
L Alrahis, M Yasin, H Saleh, B Mohammad, M Al-Qutayri
2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2019
92019
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