Chester Rebeiro
Chester Rebeiro
Indian Institute of Technology Madras
Verified email at cs.columbia.edu - Homepage
Title
Cited by
Cited by
Year
Bitslice implementation of AES
C Rebeiro, D Selvakumar, ASL Devi
International Conference on Cryptology and Network Security, 203-212, 2006
742006
Pushing the Limits of High-Speed GF(2 m ) Elliptic Curve Scalar Multiplication on FPGAs
C Rebeiro, SS Roy, D Mukhopadhyay
International Workshop on Cryptographic Hardware and Embedded Systems, 494-511, 2012
672012
High speed compact elliptic curve cryptoprocessor for FPGA platforms
C Rebeiro, D Mukhopadhyay
International Conference on Cryptology in India, 376-388, 2008
582008
Theoretical modeling of elliptic curve scalar multiplier on LUT-based FPGAs for area and speed
SS Roy, C Rebeiro, D Mukhopadhyay
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (5), 901-909, 2012
502012
Revisiting the Itoh-Tsujii inversion algorithm for FPGA platforms
C Rebeiro, SS Roy, DS Reddy, D Mukhopadhyay
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19 (8 …, 2010
402010
Power attack resistant efficient FPGA architecture for Karatsuba multiplier
C Rebeiro, D Mukhopadhyay
21st International Conference on VLSI Design (VLSID 2008), 706-711, 2008
272008
Cryptanalysis of CLEFIA using differential methods with cache trace patterns
C Rebeiro, D Mukhopadhyay
Cryptographers’ track at the RSA conference, 89-103, 2011
262011
Cache timing attacks on Clefia
C Rebeiro, D Mukhopadhyay, J Takahashi, T Fukunaga
International conference on cryptology in India, 104-118, 2009
262009
Theoretical modeling of the Itoh-Tsujii inversion algorithm for enhanced performance on k-LUT based FPGAs
SS Roy, C Rebeiro, D Mukhopadhyay
2011 Design, Automation & Test in Europe, 1-6, 2011
232011
Pinpointing cache timing attacks on AES
C Rebeiro, M Mondal, D Mukhopadhyay
2010 23rd International Conference on VLSI Design, 306-311, 2010
232010
Shakti-T: A RISC-V processor with light weight security extensions
A Menon, S Murugan, C Rebeiro, N Gala, K Veezhinathan
Proceedings of the Hardware and Architectural Support for Security and …, 2017
222017
XFC: a framework for eXploitable fault characterization in block ciphers
P Khanna, C Rebeiro, A Hazra
2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2017
222017
Timing channels in cryptography: a micro-architectural perspective
C Rebeiro, D Mukhopadhyay, S Bhattacharya
Springer, 2014
222014
An enhanced differential cache attack on CLEFIA for large cache lines
C Rebeiro, R Poddar, A Datta, D Mukhopadhyay
International Conference on Cryptology in India, 58-75, 2011
202011
Boosting profiled cache timing attacks with a priori analysis
C Rebeiro, D Mukhopadhyay
IEEE Transactions on Information Forensics and Security 7 (6), 1900-1905, 2012
172012
DRECON: DPA resistant encryption by construction
S Hajra, C Rebeiro, S Bhasin, G Bajaj, S Sharma, S Guilley, ...
International Conference on Cryptology in Africa, 420-439, 2014
162014
A parallel architecture for Koblitz curve scalar multiplications on FPGA platforms
SS Roy, C Rebeiro, D Mukhopadhyay
2012 15th Euromicro Conference on Digital System Design, 553-559, 2012
152012
Generalized high speed Itoh–Tsujii multiplicative inversion architecture for FPGAs
SS Roy, C Rebeiro, D Mukhopadhyay
Integration 45 (3), 307-315, 2012
152012
Hardware prefetchers leak: A revisit of SVF for cache-timing attacks
S Bhattacharya, C Rebeiro, D Mukhopadhyay
2012 45th Annual IEEE/ACM International Symposium on Microarchitecture …, 2012
142012
A cache trace attack on CAMELLIA
R Poddar, A Datta, C Rebeiro
International Conference on Security Aspects in Information Technology, 144-156, 2011
142011
The system can't perform the operation now. Try again later.
Articles 1–20