Chester Rebeiro - Google Scholar

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	All	Since 2015
Citations	738	509
h-index	16	12
i10-index	21	15

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Debdeep MukhopadhyayProfessor, Dept of Computer Science and Engineering, IIT Kharagpur, IndiaVerified email at cse.iitkgp.ac.in
Sujoy Sinha RoyAssistant Professor, School of Computer Science, University of BirminghamVerified email at esat.kuleuven.be
Sarani BhattacharyaPost Doctoral Research Fellow, COSIC, KU LeuvenVerified email at esat.kuleuven.be
Kamakoti VeezhinathanProfessor, Department of Computer Science, IIT MadrasVerified email at cse.iitm.ac.in
Aritra HazraDepartment of Computer Science and Engineering, Indian Institute of Technology KharagpurVerified email at cse.iitkgp.ac.in
Patanjali SLPSKUniversity of FloridaVerified email at ufl.edu
Swarup BhuniaUniversity of FloridaVerified email at ece.ufl.edu
Amit DattaSnap Inc.Verified email at snap.com
Rishabh PoddarUC BerkeleyVerified email at eecs.berkeley.edu
Prasanna Karthik VairamPhD Student, Indian Institute of Technology MadrasVerified email at cse.iitm.ac.in
Neel Talakshi GalaInCore SemiconductorsVerified email at incoresemi.com
Mainack MondalAssistant Professor at Department of Computer Science and Engineering, IIT KharagpurVerified email at cse.iitkgp.ac.in
Arjun MenonSenior Project Officer, Computer Science Department, Indian Instittue of Technology MadrasVerified email at cse.iitm.ac.in
Phuong Ha NguyeneBayVerified email at ebay.com
Keerthi KPhD Research Scholar, IIT MadrasVerified email at smail.iitm.ac.in
Punit KhannaIndian Institute of Technology MadrasVerified email at cse.iitm.ac.in
Souvik KolayMS Student, Indian Institute of Technology, KharagpurVerified email at cse.iitkgp.ernet.in
Vinod GanesanIIT MadrasVerified email at cse.iitm.ac.in
Sylvain GUILLEYTELECOM-ParisTechVerified email at secure-ic.com
Shivam BhasinNTU SingaporeVerified email at ntu.edu.sg

Chester Rebeiro

Indian Institute of Technology Madras

Verified email at cs.columbia.edu - Homepage

hardware security side-channel analysis operating systems Computer Architecture VLSI


Title Sort by citations Sort by year Sort by title	Cited by Cited by	Year
Bitslice implementation of AES C Rebeiro, D Selvakumar, ASL Devi International Conference on Cryptology and Network Security, 203-212, 2006	74	2006
Pushing the Limits of High-Speed GF(2^m) Elliptic Curve Scalar Multiplication on FPGAs C Rebeiro, SS Roy, D Mukhopadhyay International Workshop on Cryptographic Hardware and Embedded Systems, 494-511, 2012	67	2012
High speed compact elliptic curve cryptoprocessor for FPGA platforms C Rebeiro, D Mukhopadhyay International Conference on Cryptology in India, 376-388, 2008	58	2008
Theoretical modeling of elliptic curve scalar multiplier on LUT-based FPGAs for area and speed SS Roy, C Rebeiro, D Mukhopadhyay IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (5), 901-909, 2012	50	2012
Revisiting the Itoh-Tsujii inversion algorithm for FPGA platforms C Rebeiro, SS Roy, DS Reddy, D Mukhopadhyay IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19 (8 …, 2010	40	2010
Power attack resistant efficient FPGA architecture for Karatsuba multiplier C Rebeiro, D Mukhopadhyay 21st International Conference on VLSI Design (VLSID 2008), 706-711, 2008	27	2008
Cryptanalysis of CLEFIA using differential methods with cache trace patterns C Rebeiro, D Mukhopadhyay Cryptographers’ track at the RSA conference, 89-103, 2011	26	2011
Cache timing attacks on Clefia C Rebeiro, D Mukhopadhyay, J Takahashi, T Fukunaga International conference on cryptology in India, 104-118, 2009	26	2009
Theoretical modeling of the Itoh-Tsujii inversion algorithm for enhanced performance on k-LUT based FPGAs SS Roy, C Rebeiro, D Mukhopadhyay 2011 Design, Automation & Test in Europe, 1-6, 2011	23	2011
Pinpointing cache timing attacks on AES C Rebeiro, M Mondal, D Mukhopadhyay 2010 23rd International Conference on VLSI Design, 306-311, 2010	23	2010
Shakti-T: A RISC-V processor with light weight security extensions A Menon, S Murugan, C Rebeiro, N Gala, K Veezhinathan Proceedings of the Hardware and Architectural Support for Security and …, 2017	22	2017
XFC: a framework for eXploitable fault characterization in block ciphers P Khanna, C Rebeiro, A Hazra 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2017	22	2017
Timing channels in cryptography: a micro-architectural perspective C Rebeiro, D Mukhopadhyay, S Bhattacharya Springer, 2014	22	2014
An enhanced differential cache attack on CLEFIA for large cache lines C Rebeiro, R Poddar, A Datta, D Mukhopadhyay International Conference on Cryptology in India, 58-75, 2011	20	2011
Boosting profiled cache timing attacks with a priori analysis C Rebeiro, D Mukhopadhyay IEEE Transactions on Information Forensics and Security 7 (6), 1900-1905, 2012	17	2012
DRECON: DPA resistant encryption by construction S Hajra, C Rebeiro, S Bhasin, G Bajaj, S Sharma, S Guilley, ... International Conference on Cryptology in Africa, 420-439, 2014	16	2014
A parallel architecture for Koblitz curve scalar multiplications on FPGA platforms SS Roy, C Rebeiro, D Mukhopadhyay 2012 15th Euromicro Conference on Digital System Design, 553-559, 2012	15	2012
Generalized high speed Itoh–Tsujii multiplicative inversion architecture for FPGAs SS Roy, C Rebeiro, D Mukhopadhyay Integration 45 (3), 307-315, 2012	15	2012
Hardware prefetchers leak: A revisit of SVF for cache-timing attacks S Bhattacharya, C Rebeiro, D Mukhopadhyay 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture …, 2012	14	2012
A cache trace attack on CAMELLIA R Poddar, A Datta, C Rebeiro International Conference on Security Aspects in Information Technology, 144-156, 2011	14	2011

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