A kinetic model for the oxidation of silicon germanium alloys MA Rabie, YM Haddara, J Carette
Journal of applied physics 98 (7), 2005
58 2005 TSV residual Cu step height analysis by white light interferometry for 3D integration D Smith, S Singh, Y Ramnath, M Rabie, D Zhang, L England
2015 IEEE 65th Electronic Components and Technology Conference (ECTC), 578-584, 2015
24 2015 Process Development and Optimization for 3 High Aspect Ratio Via-Middle Through-Silicon Vias at Wafer Level D Zhang, D Smith, G Kumarapuram, R Giridharan, S Kakita, MA Rabie, ...
IEEE Transactions on Semiconductor Manufacturing 28 (4), 454-460, 2015
19 2015 Novel stress-free keep out zone process development for via middle TSV in 20nm planar CMOS technology MA Rabie, CS Premachandran, R Ranjan, MI Natarajan, SF Yap, D Smith, ...
IEEE International Interconnect Technology Conference, 203-206, 2014
17 2014 Successful void free gap fill of 3µm, high AR via middle, Through Silicon Vias at wafer level S Thangaraju, L England, M Rabie, D Zhang, G Kumarapuram, ...
25th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2014 …, 2014
14 2014 Structure and method of cancelling tsv-induced substrate stress MA Rabie, P Chirayarikathuveedu, MI Natarajan
US Patent App. 14/176,178, 2015
13 2015 Thermal characterization and TCAD modeling of a power amplifier in 45RFSOI for 5G mmWave applications P Paliwoda, MA Rabie, OD Restrepo, EC Silva, E Kaltalioglu, F Guarin, ...
2020 IEEE International Reliability Physics Symposium (IRPS), 1-5, 2020
7 2020 Innovative Design of Crackstop Wall for 14nm Technology Node and Beyond M Rabie, NA Polomoff, MK Hassan, VL Calero-DdelC, D Degraw, ...
2018 IEEE 68th Electronic Components and Technology Conference (ECTC), 460-466, 2018
7 2018 Optimization of Through Crackstop via using finite element modeling MA Rabie, N Polomoff
2017 18th International Conference on Thermal, Mechanical and Multi-Physics …, 2017
5 2017 Cobalt germanide contacts: growth reaction, phase formation models, and electrical properties MA Rabie, S Mirza, Y Hu, YM Haddara
Journal of Materials Science: Materials in Electronics 30, 10031-10063, 2019
3 2019 Crack trapping in semiconductor device structures NA Polomoff, M RABIE, VLC diaz del castillo, D Degraw, M Hecker
US Patent US10068859B1, 2018
3 2018 First phase to form during cobalt germanidation MA Rabie, S Mirza, V Jarvis, YM Haddara
Journal of Applied Physics 121 (14), 2017
3 2017 Effect of plasticity of copper in through silicon vias on mobility of carriers in active device areas MA Rabie
2013 Saudi International Electronics, Communications and Photonics …, 2013
3 2013 Ab Initio Electrical, Thermal Conductance, and Lorenz Numbers for Advanced CMOS InterfacesOD Restrepo, D Singh, M Rabie, P Paliwoda, EC Silva
IEEE Transactions on Electron Devices 69 (5), 2579-2584, 2022
2 2022 Optimizing die corner and optical groove corner crackstop support structures for mitigating dicing and CPI risks MA Rabie, NA Polomoff, S Pozder
2021 IEEE 71st Electronic Components and Technology Conference (ECTC), 1391-1398, 2021
2 2021 The Influence of Layer thickness on Crackstops' Mechanical Strength and Robustness NA Polomoff, MA Rabie
2021 IEEE 71st Electronic Components and Technology Conference (ECTC), 62-71, 2021
1 2021 BEoL Layout Design Considerations to Mitigate CPI Risk MA Rabie, T Raman, F Mirza, NA Polomoff, D Faruqui, S Pozder, ...
2018 IEEE International Interconnect Technology Conference (IITC), 64-66, 2018
1 2018 Thick photosensitive polyimide film side wall angle variability and scum improvement for IC packaging stress control SS Mehta, M Yeung, F Mirza, T Raman, T Longenbach, J Morgan, ...
Advances in Patterning Materials and Processes XXXV 10586, 98-110, 2018
1 2018 Method to mitigate chip package interaction risk on die corner using reinforcing tiles M Rabie
US Patent App. 15/193,700, 2017
1 2017 Mitigating transient tsv-induced ic substrate noise and resulting devices M Rabie, P Chirayarikathuveedu
US Patent App. 14/812,340, 2017
1 2017